From d21a329866a1299b180f8b14b6c73bee3d754e57 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 19 Feb 2015 14:08:04 -0800 Subject: arm(64): Replace write32() and friends with writel() This patch is a raw application of the following spatch to the directories src/arch/arm(64)?, src/mainboard/, src/soc/ and src/drivers/gic: @@ expression A, V; @@ - write32(V, A) + writel(V, A) @@ expression A, V; @@ - write16(V, A) + writew(V, A) @@ expression A, V; @@ - write8(V, A) + writeb(V, A) This replaces all uses of write{32,16,8}() with write{l,w,b}() which is currently equivalent and much more common. This is a preparatory step that will allow us to easier flip them all at once to the new write32(a,v) model. BRANCH=none BUG=chromium:451388 TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky. Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09 Signed-off-by: Patrick Georgi Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24 Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/254862 Reviewed-on: http://review.coreboot.org/9834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra124/power.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/nvidia/tegra124/power.c') diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 825b27bda9..b31d3a7781 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -48,7 +48,7 @@ static void power_ungate_partition(uint32_t id) pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; - write32(pwrgate_toggle, &pmc->pwrgate_toggle); + writel(pwrgate_toggle, &pmc->pwrgate_toggle); // Wait for the request to be accepted. while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) @@ -73,12 +73,12 @@ void power_enable_and_ungate_cpu(void) * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz), * set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s). */ - write32((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer); + writel((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer); uint32_t cntrl = read32(&pmc->cntrl); cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; cntrl |= PMC_CNTRL_CPUPWRREQ_OE; - write32(cntrl, &pmc->cntrl); + writel(cntrl, &pmc->cntrl); power_ungate_partition(POWER_PARTID_CRAIL); -- cgit v1.2.3