From 46514c2b877c29c2d7c2061a9785736e270c0c62 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 11 Jun 2020 11:59:07 -0700 Subject: treewide: Add Kconfig variable MEMLAYOUT_LD_FILE This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel Reviewed-by: Raul Rangel Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/nvidia/tegra124/memlayout.ld | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 src/soc/nvidia/tegra124/memlayout.ld (limited to 'src/soc/nvidia/tegra124/memlayout.ld') diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld new file mode 100644 index 0000000000..94b6fd8d91 --- /dev/null +++ b/src/soc/nvidia/tegra124/memlayout.ld @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + */ + +SECTIONS +{ + SRAM_START(0x40000000) + TTB(0x40000000, 16K + 32) + PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) + FMAP_CACHE(0x40005800, 2K) + PRERAM_CBFS_CACHE(0x40006000, 14K) + VBOOT2_WORK(0x40009800, 12K) + TPM_TCPA_LOG(0x4000D800, 2K) + STACK(0x4000E000, 8K) + BOOTBLOCK(0x40010000, 30K) + VERSTAGE(0x40017800, 72K) + ROMSTAGE(0x40029800, 89K) + TIMESTAMP(0x4003FC00, 1K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x80100000, 1M) + RAMSTAGE(0x80200000, 128K) + DMA_COHERENT(0x90000000, 2M) +} -- cgit v1.2.3