From 555c3b1d9b05033be0e49ec62fba43536efd410f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 19 Aug 2020 21:44:36 +0200 Subject: soc/nvidia: Drop unneeded empty lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 42 -------------------------- 1 file changed, 42 deletions(-) (limited to 'src/soc/nvidia/tegra124/lp0') diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index b7881de6a1..38a385cd29 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -12,21 +12,15 @@ enum { SYSCTR_CTLR_BASE = 0x700f0000 }; - - /* UP tag registers. */ static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); enum { UP_TAG_AVP = 0xaaaaaaaa }; - - /* Timer registers. */ static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); - - /* Clock and reset controller registers. */ static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); enum { @@ -152,14 +146,9 @@ enum { CLR_NONCPURESET = 0x1 << 29 }; - - /* Reset vector. */ - static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); - - /* Flow controller registers. */ static uint32_t *flow_ctlr_halt_cop_events_ptr = (void *)(FLOW_CTLR_BASE + 0x4); @@ -185,7 +174,6 @@ enum { RAM_REPAIR_STS = 0x1 << 1, }; - /* Power management controller registers. */ enum { PARTID_CRAIL = 0, @@ -220,8 +208,6 @@ enum { PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT }; - - /* Memory controller registers. */ static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); @@ -232,8 +218,6 @@ enum { VIDEO_PROTECT_ALLOW_TZ_WRITE_ACCESS = 0x1 << 1 }; - - /* System counter registers. */ static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); enum { @@ -243,10 +227,7 @@ enum { static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); - - /* Utility functions. */ - static __always_inline void __noreturn halt(void) { for (;;); @@ -285,10 +266,7 @@ static void udelay(unsigned int usecs) ; } - - /* Accessors. */ - static int wakeup_on_lp(void) { return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP); @@ -304,10 +282,7 @@ static unsigned int get_osc_freq(void) return (read32(clk_rst_osc_ctrl_ptr) & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT; } - - /* Clock configuration. */ - static void config_oscillator(void) { // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy @@ -416,10 +391,7 @@ static void enable_cpu_clocks(void) write32(clk_rst_clk_enb_v_set_ptr, CLK_ENB_CPUG | CLK_ENB_CPULP); } - - /* Function unit configuration. */ - static void config_core_sight(void) { // Enable the CoreSight clock. @@ -449,10 +421,7 @@ static void config_mselect(void) write32(clk_rst_rst_dev_v_clr_ptr, SWR_MSELECT_RST); } - - /* Resets. */ - static void clear_cpu_resets(void) { // Take the non-cpu of the G and LP clusters out of reset. @@ -471,10 +440,7 @@ static void clear_cpu_resets(void) CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3); } - - /* RAM repair */ - void ram_repair(void) { // Request Cluster0 RAM repair. @@ -490,9 +456,7 @@ void ram_repair(void) ; } - /* Power. */ - static void power_on_partition(unsigned int id) { uint32_t bit = 0x1 << id; @@ -544,10 +508,7 @@ static void power_on_main_cpu(void) write32(pmc_ctlr_cpupwrgood_timer_ptr, orig_timer); } - - /* Entry point. */ - void lp0_resume(void) { // If not on the AVP, reset. @@ -608,10 +569,7 @@ void lp0_resume(void) FLOW_MODE_STOP | EVENT_JTAG); } - - /* Header. */ - extern uint8_t blob_data; extern uint8_t blob_data_size; extern uint8_t blob_total_size; -- cgit v1.2.3