From 2ed0aa258f4bcbf978998ccd3a76f7b1c2d3d031 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Tue, 5 Jan 2016 20:58:58 -0700 Subject: Correct some common spelling mistakes - occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra124/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/nvidia/tegra124/clock.c') diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index de7b218e25..4c087b8539 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -389,7 +389,7 @@ clock_display(u32 frequency) /* Initialize the UART and put it on CLK_M so we can use it during clock_init(). * Will later move it to PLLP in clock_config(). The divisor must be very small - * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 + * to accommodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 * CLK_SOURCE divider to get more precision. (This might still not be enough for * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1900 has * been determined through trial and error (must lead to div 13 at 24MHz). */ -- cgit v1.2.3