From 1a8e0af78b1886acc96d1e80be5871d287d148c5 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Tue, 8 Apr 2014 20:03:40 +0800 Subject: tegra124: Setup clock PLLD by approximating display panel pixel clock. PLLD, the clock for display, was previously hard-coded to 306MHz. To support more different panels, we should calcualte PLLD by panel pixel clock configuration. Note existing pixel clock configurations for nyan* boards won't work (they used to rely on hard-coded approximated values) so the device trees are also modified. BRANCH=none BUG=chrome-os-partner:25933 TEST=emerge-nyan_big coreboot chromeos-bootimage See panel correctly initialized and got DEV screen. Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3 Original-Signed-off-by: Hung-Te Lin Original-Reviewed-on: https://chromium-review.googlesource.com/193565 (cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4) Signed-off-by: Marc Jones Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916 Reviewed-on: http://review.coreboot.org/7762 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra124/chip.h | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/nvidia/tegra124/chip.h') diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 87d043a8ca..89a8d977aa 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -89,7 +89,6 @@ struct soc_nvidia_tegra124_config { int vfront_porch; int pixel_clock; - int pll_div;; /* The minimum link configuraton settings */ u32 lane_count; -- cgit v1.2.3