From c53a0aaa594903194ecd25b07b270b424a45cb8a Mon Sep 17 00:00:00 2001 From: zhiyong tao Date: Wed, 4 May 2022 10:46:12 +0800 Subject: soc/mediatek/mt8186: Change the power-down time slot from 0xA to 0xF PMIC_CPSDSA4[4:0] controls the power-down at the specified time slot. Setting it to 0xA would cause an extra delay of 20ms compared to 0xF. The value of time slot is from 0x0 to 0x1F which represents the delay when reset occurs. To avoid the delay, change the value from 0xA to 0xF. This modification is based on chapter 3.7 in the MT8186 functional specification. BUG=b:218630683, b:218630684 TEST=the power-off waveform is correct. Signed-off-by: zhiyong tao Change-Id: I537fe87740f0f8c25b923d7d536e81503b71762b Reviewed-on: https://review.coreboot.org/c/coreboot/+/64038 Reviewed-by: Rex-BC Chen Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8186/mt6366.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek') diff --git a/src/soc/mediatek/mt8186/mt6366.c b/src/soc/mediatek/mt8186/mt6366.c index 8dd2997807..af5403a55d 100644 --- a/src/soc/mediatek/mt8186/mt6366.c +++ b/src/soc/mediatek/mt8186/mt6366.c @@ -807,8 +807,8 @@ static void wk_sleep_voltage_by_ddr(void) static void wk_power_down_seq(void) { mt6366_protect_control(false); - /* Set VPROC12 sequence to VA12 */ - pwrap_write_field(PMIC_CPSDSA4, 0xA, 0x1F, 0); + /* Set VPROC12 power-down time slot to 0xF to avoid 20ms delay */ + pwrap_write_field(PMIC_CPSDSA4, 0xF, 0x1F, 0); mt6366_protect_control(true); } -- cgit v1.2.3