From 7c71b9498446ca45ac3b00af1c07eddfa5b89930 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Tue, 27 Aug 2024 13:19:35 +0800 Subject: soc/mediatek/common/pcie: Use clr/setbits32p Use clr/setbits32p to make code cleaner. BUG=none TEST=emerge-cherry coreboot Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Jianjun Wang --- src/soc/mediatek/common/pcie.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'src/soc/mediatek') diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c07cc4f748..39714e161a 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -266,20 +266,14 @@ void mtk_pcie_domain_enable(struct device *dev) uint32_t val; /* Set as RC mode */ - val = read32p(conf->base + PCIE_SETTING_REG); - val |= PCIE_RC_MODE; - write32p(conf->base + PCIE_SETTING_REG, val); + setbits32p(conf->base + PCIE_SETTING_REG, PCIE_RC_MODE); /* Set class code */ - val = read32p(conf->base + PCIE_PCI_IDS_1); - val &= ~GENMASK(31, 8); - val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(conf->base + PCIE_PCI_IDS_1, val); + clrsetbits32p(conf->base + PCIE_PCI_IDS_1, GENMASK(31, 8), + PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8)); /* Mask all INTx interrupts */ - val = read32p(conf->base + PCIE_INT_ENABLE_REG); - val &= ~PCIE_INTX_ENABLE; - write32p(conf->base + PCIE_INT_ENABLE_REG, val); + clrbits32p(conf->base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE); perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n", -- cgit v1.2.3