From 42b7b77571bd45f28850eb66a17f0ef91f995f28 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 8 Apr 2019 20:10:23 +0800 Subject: mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootup Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window earlier than with other DDR type. So need change the DQS starting offset to increase the scan range of RX window. BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Julius Werner Reviewed-by: Huayang Duan --- src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/mediatek') diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 6dc8fa6588..05f793ec4b 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -32,7 +32,7 @@ enum { enum { FIRST_DQ_DELAY = 0, - FIRST_DQS_DELAY = -10, + FIRST_DQS_DELAY = -16, MAX_DQDLY_TAPS = 16, MAX_RX_DQDLY_TAPS = 63, }; -- cgit v1.2.3