From 27be90424b7cb8fd51c7ff6b6812601b9d091b6b Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidi.lin@mediatek.com>
Date: Thu, 25 Mar 2021 17:50:14 +0800
Subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache

Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/mt8195/Makefile.inc     |  1 +
 src/soc/mediatek/mt8195/mmu_operations.c | 31 +++++++++++++++++++++++++++++++
 src/soc/mediatek/mt8195/soc.c            |  2 ++
 3 files changed, 34 insertions(+)
 create mode 100644 src/soc/mediatek/mt8195/mmu_operations.c

(limited to 'src/soc/mediatek')

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 796c335ea2..f848f7bf33 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -35,6 +35,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c
 ramstage-y += emi.c
 ramstage-y += ../common/flash_controller.c
 ramstage-y += ../common/gpio.c gpio.c
+ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += soc.c
diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c
new file mode 100644
index 0000000000..7018093dd9
--- /dev/null
+++ b/src/soc/mediatek/mt8195/mmu_operations.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/mcucfg.h>
+#include <soc/mmu_operations.h>
+#include <soc/symbols.h>
+
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
+
+void mtk_soc_disable_l2c_sram(void)
+{
+	unsigned long v;
+
+	SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
+	dsb();
+
+	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+	v |= (0xf << 4);
+	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+	dsb();
+
+	do {
+		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+	} while (((v >> 0x4) & 0xf) != 0xf);
+
+	SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
+	dsb();
+}
diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c
index af28dd4397..4c98a662f9 100644
--- a/src/soc/mediatek/mt8195/soc.c
+++ b/src/soc/mediatek/mt8195/soc.c
@@ -2,6 +2,7 @@
 
 #include <device/device.h>
 #include <soc/emi.h>
+#include <soc/mmu_operations.h>
 #include <symbols.h>
 
 static void soc_read_resources(struct device *dev)
@@ -11,6 +12,7 @@ static void soc_read_resources(struct device *dev)
 
 static void soc_init(struct device *dev)
 {
+	mtk_mmu_disable_l2c_sram();
 }
 
 static struct device_operations soc_ops = {
-- 
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