From 19e961e83c4200de78cbbb9e8e5800c535619a42 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Mon, 21 Oct 2019 16:47:18 +0800 Subject: soc/mediatek/mt8183: fine tune the phy timing To fix MIPI D-PHY test failure, the hs-prepare should be less than LimitMin from spec, and we have to enlarge TEOT margin. BUG=b:138344447 BRANCH=kukui TEST=Boots correctly on kukui Change-Id: If91e7a546866299f02432be27fe778be5d7bdc5f Signed-off-by: Jitao Shi Reviewed-on: https://review.coreboot.org/c/coreboot/+/36222 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/common/dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek') diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 679bec8d75..2b4fac7d42 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -81,9 +81,9 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) memset(phy_timing, 0, sizeof(*phy_timing)); phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((50 + 5 * ui), cycle_time); phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 77), cycle_time); phy_timing->ta_go = 4U * phy_timing->lpx; phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; -- cgit v1.2.3