From 0d13e80852832368ac7ed51f8d04011a71ddbbc2 Mon Sep 17 00:00:00 2001 From: Liya Li Date: Sat, 23 Jul 2022 14:23:04 +0800 Subject: soc/mediatek/mt8188: Add SPI support The gpios and the tick delay register are different between MT8188 and previous MediaTek SoCs, so we need to add this patch to support SPI. TEST=build pass BUG=b:236331724 Signed-off-by: Liya Li Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185 Reviewed-by: Yu-Ping Wu Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8188/Makefile.inc | 2 +- src/soc/mediatek/mt8188/include/soc/spi.h | 15 ++++++ src/soc/mediatek/mt8188/spi.c | 86 +++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+), 1 deletion(-) (limited to 'src/soc/mediatek') diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 827b4318e6..d82b19cda7 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -4,7 +4,7 @@ all-y += ../common/flash_controller.c all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-y += ../common/i2c.c i2c.c all-y += ../common/pll.c pll.c -all-$(CONFIG_SPI_FLASH) += spi.c +all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c all-y += ../common/timer.c ../common/timer_prepare.c all-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8188/include/soc/spi.h b/src/soc/mediatek/mt8188/include/soc/spi.h index 53aba25243..50ab6127b2 100644 --- a/src/soc/mediatek/mt8188/include/soc/spi.h +++ b/src/soc/mediatek/mt8188/include/soc/spi.h @@ -8,8 +8,23 @@ #ifndef MTK_MT8188_SPI_H #define MTK_MT8188_SPI_H +#include #include +#define SPI_BUS_NUMBER 6 + +#define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cmd_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 32, 16) +DEFINE_BITFIELD(SPI_TICK_DLY, 24, 22) + void mtk_snfc_init(void); #endif diff --git a/src/soc/mediatek/mt8188/spi.c b/src/soc/mediatek/mt8188/spi.c index 5c35e6884e..7297f6627b 100644 --- a/src/soc/mediatek/mt8188/spi.c +++ b/src/soc/mediatek/mt8188/spi.c @@ -5,11 +5,40 @@ * Chapter number: 5.8, 5.19 */ +#include #include #include #include #include #include +#include + +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPIM0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPIM1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SPIM2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(DPI_D12), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(GPIO12), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(GPIO00), + }, +}; struct pad_func { gpio_t gpio; @@ -18,6 +47,47 @@ struct pad_func { }; #define PAD_FUNC_SEL(name, func, sel) {GPIO(name), PAD_##name##_FUNC_##func, sel} +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {GPIO(name), 0} + +static const struct pad_func pad_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPIM0_MISO, SPIM0_MISO), + PAD_FUNC_GPIO(SPIM0_CSB), + PAD_FUNC(SPIM0_MOSI, SPIM0_MOSI), + PAD_FUNC(SPIM0_CLK, SPIM0_CLK), + }, + { + PAD_FUNC(SPIM1_MISO, SPIM1_MISO), + PAD_FUNC_GPIO(SPIM1_CSB), + PAD_FUNC(SPIM1_MOSI, SPIM1_MOSI), + PAD_FUNC(SPIM1_CLK, SPIM1_CLK), + }, + { + PAD_FUNC(SPIM2_MISO, SPIM2_MISO), + PAD_FUNC_GPIO(SPIM2_CSB), + PAD_FUNC(SPIM2_MOSI, SPIM2_MOSI), + PAD_FUNC(SPIM2_CLK, SPIM2_CLK), + }, + { + PAD_FUNC(DPI_D15, SPIM3_MISO), + PAD_FUNC_GPIO(DPI_D12), + PAD_FUNC(DPI_D14, SPIM3_MOSI), + PAD_FUNC(DPI_D13, SPIM3_CLK), + }, + { + PAD_FUNC(GPIO15, SPIM4_MISO), + PAD_FUNC_GPIO(GPIO12), + PAD_FUNC(GPIO14, SPIM4_MOSI), + PAD_FUNC(GPIO13, SPIM4_CLK), + }, + { + PAD_FUNC(GPIO03, SPIM5_MISO), + PAD_FUNC_GPIO(GPIO00), + PAD_FUNC(GPIO02, SPIM5_MOSI), + PAD_FUNC(GPIO01, SPIM5_CLK), + }, +}; static const struct pad_func nor_pinmux[4] = { /* GPIO 125 ~ 128 */ @@ -38,12 +108,28 @@ void mtk_snfc_init(void) } } +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr; + + ptr = pad_funcs[bus]; + + for (unsigned int i = 0; i < SPI_BUS_NUMBER; i++) + gpio_set_mode(ptr[i].gpio, ptr[i].func); +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, { .ctrlr = &spi_flash_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, -- cgit v1.2.3