From 8cb9641eca5d24048bf9e9a5a4707cae1e26d366 Mon Sep 17 00:00:00 2001 From: Jarried Lin Date: Sun, 14 Jul 2024 18:57:15 +0800 Subject: soc/mediatek/mt8196: Add a stub implementation of the MT8196 SoC Add new folder and basic drivers for Mediatek SoC 'MT8196'. Refer to MT8196_Chromebook_Application_Processor_Datasheet_V1.0 for MT8196 SPEC detail. This patch also enables UART and ARM arch timer. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Change-Id: I8190253ed000db879b04a806ca0bdf29c14be806 Signed-off-by: Jarried Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/83572 Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8196/spi.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 src/soc/mediatek/mt8196/spi.c (limited to 'src/soc/mediatek/mt8196/spi.c') diff --git a/src/soc/mediatek/mt8196/spi.c b/src/soc/mediatek/mt8196/spi.c new file mode 100644 index 0000000000..11bbb5f143 --- /dev/null +++ b/src/soc/mediatek/mt8196/spi.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 13.9 + */ + +#include +#include +#include + +static const struct spi_ctrlr spi_flash_ctrlr = { + .max_xfer_size = 65535, +}; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_flash_ctrlr, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- cgit v1.2.3