From 946b2556f90df6adc220edb006b4dc03f6440f28 Mon Sep 17 00:00:00 2001 From: Guangjie Song Date: Wed, 24 Jul 2024 16:45:19 +0800 Subject: soc/mediatek/mt8196: Add PLL and clock init support Add PLL and clock init code, frequency meter and APIs for raising little CPU frequency and set tvdpll frequency. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84495 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin --- src/soc/mediatek/mt8196/bootblock.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/mediatek/mt8196/bootblock.c') diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 1b1f09f07c..19b90eee45 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -3,11 +3,14 @@ #include #include #include +#include #include void bootblock_soc_init(void) { mtk_mmu_init(); mtk_wdt_init(); + mt_pll_init(); + mt_pll_post_init(); early_init_clear(); } -- cgit v1.2.3