From d239aaf741372594fd31e452300816aeaae09000 Mon Sep 17 00:00:00 2001 From: Xi Chen Date: Fri, 21 Jan 2022 13:59:59 +0800 Subject: src/mediatek: Refactor dramc_param to share more structures The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To prevent code duplication, move it as well as other related structs and enums to a common header. Signed-off-by: Xi Chen Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8192/include/soc/dramc_param.h | 60 ----------------------- 1 file changed, 60 deletions(-) (limited to 'src/soc/mediatek/mt8192') diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h index 09501b0ca5..a5357c9cd2 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -15,49 +15,6 @@ #define DRAMC_PARAM_HEADER_VERSION 7 -enum DRAMC_PARAM_STATUS_CODES { - DRAMC_SUCCESS = 0, - DRAMC_ERR_INVALID_VERSION, - DRAMC_ERR_INVALID_SIZE, - DRAMC_ERR_INVALID_FLAGS, - DRAMC_ERR_RECALIBRATE, - DRAMC_ERR_INIT_DRAM, - DRAMC_ERR_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_1ST_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_2ND_COMPLEX_RW_MEM_TEST, - DRAMC_ERR_FAST_CALIBRATION, -}; - -enum SDRAM_DVFS_FLAG { - DRAMC_DISABLE_DVFS, - DRAMC_ENABLE_DVFS, -}; - -enum SDRAM_DDR_TYPE { - DDR_TYPE_DISCRETE, - DDR_TYPE_EMCP, -}; - -enum SDRAM_DDR_GEOMETRY_TYPE { - DDR_TYPE_2CH_2RK_4GB_2_2, - DDR_TYPE_2CH_2RK_6GB_3_3, - DDR_TYPE_2CH_2RK_8GB_4_4_BYTE, - DDR_TYPE_2CH_1RK_4GB_4_0, - DDR_TYPE_2CH_2RK_6GB_2_4, - DDR_TYPE_2CH_2RK_8GB_4_4, -}; - -enum SDRAM_VOLTAGE_TYPE { - SDRAM_VOLTAGE_NVCORE_NVDRAM, - SDRAM_VOLTAGE_HVCORE_HVDRAM, - SDRAM_VOLTAGE_LVCORE_LVDRAM, -}; - -struct sdram_info { - u32 ddr_type; /* SDRAM_DDR_TYPE */ - u32 ddr_geometry; /* SDRAM_DDR_GEOMETRY_TYPE */ -}; - struct sdram_params { u32 rank_num; u16 num_dlycell_perT; @@ -105,23 +62,6 @@ struct sdram_params { u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4]; }; -struct emi_mdl { - u32 cona_val; - u32 conh_val; - u32 conf_val; - u32 chn_cona_val; -}; - -struct ddr_base_info { - u32 config_dvfs; /* SDRAM_DVFS_FLAG */ - struct sdram_info sdram; - u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ - u32 support_ranks; - u64 rank_size[RANK_MAX]; - struct emi_mdl emi_config; - DRAM_CBT_MODE_T cbt_mode[RANK_MAX]; -}; - struct dramc_data { struct ddr_base_info ddr_info; struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; -- cgit v1.2.3