From 9ee02095fa1b5c532f758e287401423138687b56 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Tue, 22 Sep 2020 19:56:20 +0800 Subject: mb/google/asurada: Implement board-specific regulator controls Currently, five regulator controls are implemented for DRAM calibration and DVFS feature. The regulators for VCORE and VM18 are controlled by MT6359. The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360 via EC. BUG=b:147789962 BRANCH=none TEST=verified with DRAM driver Signed-off-by: Yidi Lin Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8192/include/soc/mt6360.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 src/soc/mediatek/mt8192/include/soc/mt6360.h (limited to 'src/soc/mediatek/mt8192') diff --git a/src/soc/mediatek/mt8192/include/soc/mt6360.h b/src/soc/mediatek/mt8192/include/soc/mt6360.h new file mode 100644 index 0000000000..a6ee76c08b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mt6360.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6360_H__ +#define __SOC_MEDIATEK_MT6360_H__ + +enum mt6360_regulator_id { + MT6360_LDO3 = 0, + MT6360_LDO5, + MT6360_LDO6, + MT6360_LDO7, + MT6360_BUCK1, + MT6360_BUCK2, + MT6360_REGULATOR_COUNT, +}; + +#endif /* __SOC_MEDIATEK_MT6360_H__ */ -- cgit v1.2.3