From 1a5d279120a93986f4272072b6c55c81b82bafe7 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Thu, 18 Mar 2021 14:13:56 +0800 Subject: soc/mediatek/mt8192: devapc: Add SCP domain setting Configure SCP domain from 0 to 3 and lock it to prevent changing it unexpectedly. BUG=b:163300760 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Idccb001f0cf58492f7f1655203106470637b9b82 Signed-off-by: Tinghan Shen Reviewed-on: https://review.coreboot.org/c/coreboot/+/51622 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8192/devapc.c | 9 +++++++++ src/soc/mediatek/mt8192/include/soc/addressmap.h | 1 + src/soc/mediatek/mt8192/include/soc/devapc.h | 5 +++++ 3 files changed, 15 insertions(+) (limited to 'src/soc/mediatek/mt8192') diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c index 542c05f633..327896b10a 100644 --- a/src/soc/mediatek/mt8192/devapc.c +++ b/src/soc/mediatek/mt8192/devapc.c @@ -68,6 +68,14 @@ static void fmem_master_init(uintptr_t base) FOUR_BIT_DOM_REMAP_7, MAS_DOMAIN_15); } +static void scp_master_init(uintptr_t base) +{ + write32(getreg(base, SCP_DOM), MAS_DOMAIN_3); + + /* Let SCP_DOM register be read-only for security */ + write32(getreg(base, ONETIME_LOCK), 0x1); +} + struct devapc_init { uintptr_t base; void (*init)(uintptr_t base); @@ -77,6 +85,7 @@ struct devapc_init { { DEVAPC_PERI2_AO_BASE, NULL }, { DEVAPC_PERI_PAR_AO_BASE, NULL }, { DEVAPC_FMEM_AO_BASE, fmem_master_init }, + { SCP_CFG_BASE, scp_master_init }, }; void dapc_init(void) diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 3a07802f8d..51a89e1cf3 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -41,6 +41,7 @@ enum { DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, + SCP_CFG_BASE = IO_PHYS + 0x00700000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, DPM_CFG_BASE = IO_PHYS + 0x00940000, diff --git a/src/soc/mediatek/mt8192/include/soc/devapc.h b/src/soc/mediatek/mt8192/include/soc/devapc.h index 7ba6d46477..fd332dbd15 100644 --- a/src/soc/mediatek/mt8192/include/soc/devapc.h +++ b/src/soc/mediatek/mt8192/include/soc/devapc.h @@ -21,6 +21,11 @@ enum devapc_ao_offset { AO_APC_CON = 0x0F00, }; +enum scp_offset { + SCP_DOM = 0xA5080, + ONETIME_LOCK = 0xA5104, +}; + /* INFRA */ DEFINE_BIT(SCP_SSPM_SEC, 3) DEFINE_BIT(CPU_EB_SEC, 4) -- cgit v1.2.3