From be404c22aa8d9675d1b4b62fd188aee5aef01f88 Mon Sep 17 00:00:00 2001 From: "TingHan.Shen" Date: Fri, 20 Nov 2020 14:42:23 +0800 Subject: soc/mediatek/mt8192: Init SSPM SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. Signed-off-by: TingHan.Shen Change-Id: Ia834852af50e9e7e1b1222ed1e2be20e43139c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47786 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/include/soc/addressmap.h | 2 ++ src/soc/mediatek/mt8192/include/soc/sspm.h | 14 ++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 src/soc/mediatek/mt8192/include/soc/sspm.h (limited to 'src/soc/mediatek/mt8192/include') diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 2e8ac9e715..829712926d 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -27,6 +27,8 @@ enum { PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + SSPM_SRAM_BASE = IO_PHYS + 0x00400000, + SSPM_CFG_BASE = IO_PHYS + 0x00440000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, DPM_CFG_BASE = IO_PHYS + 0x00940000, diff --git a/src/soc/mediatek/mt8192/include/soc/sspm.h b/src/soc/mediatek/mt8192/include/soc/sspm.h new file mode 100644 index 0000000000..5749fa4be3 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/sspm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_SSPM_H +#define SOC_MEDIATEK_MT8192_SSPM_H + +#include +#include + +struct mt8192_sspm_regs { + u32 sw_rstn; +}; +static struct mt8192_sspm_regs *const mt8192_sspm = (void *)SSPM_CFG_BASE; +void sspm_init(void); +#endif /* SOC_MEDIATEK_MT8192_SSPM_H */ -- cgit v1.2.3