From 86b3bf10e60c137b01b81a37ce9827757f6af42d Mon Sep 17 00:00:00 2001
From: Weiyi Lu <weiyi.lu@mediatek.com>
Date: Fri, 19 Jun 2020 15:28:55 +0800
Subject: soc/mediatek: Add function to raise the CPU frequency of MT8192

Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8192/include/soc/pll.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/mediatek/mt8192/include')

diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h
index 442aa30877..43c2528994 100644
--- a/src/soc/mediatek/mt8192/include/soc/pll.h
+++ b/src/soc/mediatek/mt8192/include/soc/pll.h
@@ -249,6 +249,7 @@ enum {
 
 	MCU_MUX_MASK = 0x3 << 9,
 	MCU_MUX_SRC_PLL = 0x1 << 9,
+	MCU_MUX_SRC_DIV_PLL1 = 0x2 << 9,
 };
 
 enum {
-- 
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