From 22f8370def35d33a67189b9643114bf3e00e2c47 Mon Sep 17 00:00:00 2001 From: Hsin-Hsiung Wang Date: Fri, 29 May 2020 19:46:14 +0800 Subject: soc/mediatek/mt8192: add pmif driver MT8192 uses power management interface (PMIF) to access pmics by spmi and spi, so we add pmif driver to control pmics. BUG=b:155253454 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang Change-Id: I32fc28f72d9522133baa06f9d67c383f814d862c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45398 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8192/include/soc/addressmap.h | 5 +- src/soc/mediatek/mt8192/include/soc/pll.h | 6 +- src/soc/mediatek/mt8192/include/soc/pmif.h | 172 +++++++++++++++++++++++ src/soc/mediatek/mt8192/include/soc/pmif_spi.h | 125 ++++++++++++++++ src/soc/mediatek/mt8192/include/soc/pmif_spmi.h | 99 +++++++++++++ src/soc/mediatek/mt8192/include/soc/pmif_sw.h | 45 ++++++ src/soc/mediatek/mt8192/include/soc/spmi.h | 50 +++++++ 7 files changed, 500 insertions(+), 2 deletions(-) create mode 100644 src/soc/mediatek/mt8192/include/soc/pmif.h create mode 100644 src/soc/mediatek/mt8192/include/soc/pmif_spi.h create mode 100644 src/soc/mediatek/mt8192/include/soc/pmif_spmi.h create mode 100644 src/soc/mediatek/mt8192/include/soc/pmif_sw.h create mode 100644 src/soc/mediatek/mt8192/include/soc/spmi.h (limited to 'src/soc/mediatek/mt8192/include') diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e0cd5364a3..69d3157702 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -21,7 +21,10 @@ enum { GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, APMIXED_BASE = IO_PHYS + 0x0000C000, - PWRAP_BASE = IO_PHYS + 0x0000D000, + PMIF_SPI_BASE = IO_PHYS + 0x00026000, + PMIF_SPMI_BASE = IO_PHYS + 0x00027000, + PMICSPI_MST_BASE = IO_PHYS + 0x00028000, + SPMI_MST_BASE = IO_PHYS + 0x00029000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index d5a9cf9a3e..09c4c47118 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -178,7 +178,11 @@ struct mtk_apmixed_regs { u32 mfgpll_con2; u32 mfgpll_con3; u32 ap_pllgp1_con2; - u32 reserved2[33]; + u32 reserved2[13]; + u32 ulposc1_con0; + u32 ulposc1_con1; + u32 ulposc1_con2; + u32 reserved3[17]; u32 ap_pllgp2_con0; /* 0x0300 */ u32 ap_pllgp2_con1; u32 univpll_con0; diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h new file mode 100644 index 0000000000..fe3def020a --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MT8192_SOC_PMIF_H__ +#define __MT8192_SOC_PMIF_H__ + +#include + +enum { + PMIF_CMD_REG_0, + PMIF_CMD_REG, + PMIF_CMD_EXT_REG, + PMIF_CMD_EXT_REG_LONG, +}; + +struct mtk_pmif_regs { + u32 init_done; + u32 reserved1[5]; + u32 inf_busy_sta; + u32 other_busy_sta_0; + u32 other_busy_sta_1; + u32 inf_en; + u32 other_inf_en; + u32 inf_cmd_per_0; + u32 inf_cmd_per_1; + u32 inf_cmd_per_2; + u32 inf_cmd_per_3; + u32 inf_max_bytecnt_per_0; + u32 inf_max_bytecnt_per_1; + u32 inf_max_bytecnt_per_2; + u32 inf_max_bytecnt_per_3; + u32 staupd_ctrl; + u32 reserved2[48]; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 reserved3[13]; + u32 arb_en; + u32 reserved4[34]; + u32 lat_cnter_en; + u32 lat_limit_loading; + u32 lat_limit_0; + u32 lat_limit_1; + u32 lat_limit_2; + u32 lat_limit_3; + u32 lat_limit_4; + u32 lat_limit_5; + u32 lat_limit_6; + u32 lat_limit_7; + u32 lat_limit_8; + u32 lat_limit_9; + u32 reserved5[99]; + u32 crc_ctrl; + u32 crc_sta; + u32 sig_mode; + u32 pmic_sig_addr; + u32 pmic_sig_val; + u32 reserved6[2]; + u32 cmdissue_en; + u32 reserved7[10]; + u32 timer_ctrl; + u32 timer_sta; + u32 sleep_protection_ctrl; + u32 reserved8[5]; + u32 spi_mode_ctrl; + u32 reserved9[2]; + u32 pmic_eint_sta_addr; + u32 reserved10[2]; + u32 irq_event_en_0; + u32 irq_flag_raw_0; + u32 irq_flag_0; + u32 irq_clr_0; + u32 reserved11[502]; + u32 swinf_0_acc; + u32 swinf_0_wdata_31_0; + u32 swinf_0_wdata_63_32; + u32 reserved12[2]; + u32 swinf_0_rdata_31_0; + u32 swinf_0_rdata_63_32; + u32 reserved13[2]; + u32 swinf_0_vld_clr; + u32 swinf_0_sta; + u32 reserved14[5]; + u32 swinf_1_acc; + u32 swinf_1_wdata_31_0; + u32 swinf_1_wdata_63_32; + u32 reserved15[2]; + u32 swinf_1_rdata_31_0; + u32 swinf_1_rdata_63_32; + u32 reserved16[2]; + u32 swinf_1_vld_clr; + u32 swinf_1_sta; + u32 reserved17[5]; + u32 swinf_2_acc; + u32 swinf_2_wdata_31_0; + u32 swinf_2_wdata_63_32; + u32 reserved18[2]; + u32 swinf_2_rdata_31_0; + u32 swinf_2_rdata_63_32; + u32 reserved19[2]; + u32 swinf_2_vld_clr; + u32 swinf_2_sta; + u32 reserved20[5]; + u32 swinf_3_acc; + u32 swinf_3_wdata_31_0; + u32 swinf_3_wdata_63_32; + u32 reserved21[2]; + u32 swinf_3_rdata_31_0; + u32 swinf_3_rdata_63_32; + u32 reserved22[2]; + u32 swinf_3_vld_clr; + u32 swinf_3_sta; + u32 reserved23[133]; +}; + +check_member(mtk_pmif_regs, inf_busy_sta, 0x18); +check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); +check_member(mtk_pmif_regs, arb_en, 0x0150); +check_member(mtk_pmif_regs, lat_cnter_en, 0x1DC); +check_member(mtk_pmif_regs, crc_ctrl, 0x398); +check_member(mtk_pmif_regs, cmdissue_en, 0x3B4); +check_member(mtk_pmif_regs, timer_ctrl, 0x3E0); +check_member(mtk_pmif_regs, spi_mode_ctrl, 0x400); +check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x40C); +check_member(mtk_pmif_regs, irq_event_en_0, 0x418); +check_member(mtk_pmif_regs, swinf_0_acc, 0xC00); + +#define PMIF_SPMI_AP_CHAN (PMIF_SPMI_BASE + 0xC80) +#define PMIF_SPI_AP_CHAN (PMIF_SPI_BASE + 0xC80) + +struct chan_regs { + u32 ch_send; + u32 wdata; + u32 reserved12[3]; + u32 rdata; + u32 reserved13[3]; + u32 ch_rdy; + u32 ch_sta; +}; + +struct pmif { + struct mtk_pmif_regs *mtk_pmif; + struct chan_regs *ch; + u32 swinf_no; + u32 mstid; + u32 pmifid; + void (*read)(struct pmif *arb, u32 slvid, u32 reg, u32 *data); + void (*write)(struct pmif *arb, u32 slvid, u32 reg, u32 data); + u32 (*read_field)(struct pmif *arb, u32 slvid, u32 reg, u32 mask, u32 shift); + void (*write_field)(struct pmif *arb, u32 slvid, u32 reg, u32 val, u32 mask, u32 shift); + int (*is_pmif_init_done)(struct pmif *arb); +}; + +enum { + PMIF_SPI, + PMIF_SPMI, +}; + +enum { + E_IO = 1, /* I/O error */ + E_BUSY, /* Device or resource busy */ + E_NODEV, /* No such device */ + E_INVAL, /* Invalid argument */ + E_OPNOTSUPP, /* Operation not supported on transport endpoint */ + E_TIMEOUT, /* Wait for idle time out */ + E_READ_TEST_FAIL, /* SPI read fail */ + E_SPI_INIT_RESET_SPI, /* Reset SPI fail */ + E_SPI_INIT_SIDLY, /* SPI edge calibration fail */ +}; + +extern struct pmif *get_pmif_controller(int inf, int mstid); +extern int mtk_pmif_init(void); +#endif /*__MT8192_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h new file mode 100644 index 0000000000..426aa3bf28 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spi.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ + +#include +#include + +struct mt8192_pmicspi_mst_regs { + u32 reserved1[4]; + u32 other_busy_sta_0; + u32 wrap_en; + u32 reserved2[2]; + u32 man_en; + u32 man_acc; + u32 reserved3[3]; + u32 mux_sel; + u32 reserved4[3]; + u32 dio_en; + u32 rddmy; + u32 cslext_write; + u32 cslext_read; + u32 cshext_write; + u32 cshext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 si_sampling_ctrl; +}; + +check_member(mt8192_pmicspi_mst_regs, other_busy_sta_0, 0x10); +check_member(mt8192_pmicspi_mst_regs, man_en, 0x20); +check_member(mt8192_pmicspi_mst_regs, mux_sel, 0x34); +check_member(mt8192_pmicspi_mst_regs, dio_en, 0x44); + +static struct mt8192_pmicspi_mst_regs * const mtk_pmicspi_mst = (void *)PMICSPI_MST_BASE; + +struct mt8192_iocfg_lm_regs { + u32 reserved[4]; + u32 drv_cfg1; +}; +check_member(mt8192_iocfg_lm_regs, drv_cfg1, 0x10); + +static struct mt8192_iocfg_lm_regs * const mtk_iocfg_lm = (void *)IOCFG_LM_BASE; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0032, + PMIC_DRV_CON1 = PMIC_BASE + 0x003a, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0042, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040c, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040e, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0424, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0426, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044a, + PMIC_INT_STA = PMIC_BASE + 0x0452, + PMIC_AUXADC_ADC7 = PMIC_BASE + 0x1096, + PMIC_AUXADC_ADC10 = PMIC_BASE + 0x109c, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, +}; + +#define PMIF_SPI_HW_INF 0x307F +#define PMIF_SPI_MD BIT(8) +#define PMIF_SPI_AP_SECURE BIT(9) +#define PMIF_SPI_AP BIT(10) +#define PMIF_SPI_STAUPD BIT(14) +#define PMIF_SPI_TSX_HW BIT(19) +#define PMIF_SPI_DCXO_HW BIT(20) + +#define DEFAULT_SLVID 0 + +#define PMIF_CMD_STA BIT(2) +#define SPIMST_STA BIT(9) + +enum { + SPI_CLK = 0x1, + SPI_CSN = 0x1 << 1, + SPI_MOSI = 0x1 << 2, + SPI_MISO = 0x1 << 3, + SPI_FILTER = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, + SPI_SMT = SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO, + SPI_PULL_DISABLE = (SPI_CLK | SPI_CSN | SPI_MOSI | SPI_MISO) << 4, +}; + +enum { + IO_4_MA = 0x1, + SLV_IO_4_MA = 0x8, +}; + +enum { + SPI_CLK_SHIFT = 0, + SPI_CSN_SHIFT = 4, + SPI_MOSI_SHIFT = 8, + SPI_MISO_SHIFT = 12, + SPI_DRIVING = SLV_IO_4_MA << SPI_CLK_SHIFT | SLV_IO_4_MA << SPI_CSN_SHIFT | + SLV_IO_4_MA << SPI_MOSI_SHIFT | SLV_IO_4_MA << SPI_MISO_SHIFT, +}; + +enum { + OP_WR = 0x1, + OP_CSH = 0x0, + OP_CSL = 0x1, + OP_OUTS = 0x8, +}; + +enum { + DEFAULT_VALUE_READ_TEST = 0x5aa5, + WRITE_TEST_VALUE = 0xa55a, +}; + +enum { + DUMMY_READ_CYCLES = 0x8, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING, +}; +extern int pmif_spi_init(struct pmif *arb); +#endif /* __SOC_MEDIATEK_MT8192_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h new file mode 100644 index 0000000000..d89a072123 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_spmi.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SPMI_H__ +#define __PMIF_SPMI_H__ + +#include + +#define DEFAULT_VALUE_READ_TEST (0x5a) +#define DEFAULT_VALUE_WRITE_TEST (0xa5) + +/* indicate which number SW channel start, by project */ +#define PMIF_SPMI_SW_CHAN BIT(6) +#define PMIF_SPMI_INF 0x2F7 + +struct mtk_rgu_regs { + u32 reserved[36]; + u32 wdt_swsysrst2; +}; +check_member(mtk_rgu_regs, wdt_swsysrst2, 0x90); + +struct mtk_iocfg_bm_regs { + u32 reserved[8]; + u32 drv_cfg2; +}; +check_member(mtk_iocfg_bm_regs, drv_cfg2, 0x20); + +struct mtk_spm_regs { + u32 poweron_config_en; + u32 reserved[263]; + u32 ulposc_con; +}; +check_member(mtk_spm_regs, ulposc_con, 0x420); + +struct mtk_spmi_mst_reg { + u32 op_st_ctrl; + u32 grp_id_en; + u32 op_st_sta; + u32 mst_sampl; + u32 mst_req_en; + u32 reserved1[11]; + u32 rec_ctrl; + u32 rec0; + u32 rec1; + u32 rec2; + u32 rec3; + u32 rec4; + u32 reserved2[41]; + u32 mst_dbg; +}; + +check_member(mtk_spmi_mst_reg, rec_ctrl, 0x40); +check_member(mtk_spmi_mst_reg, mst_dbg, 0xfc); + +#define mtk_rug ((struct mtk_rgu_regs *)RGU_BASE) +#define mtk_iocfg_bm ((struct mtk_iocfg_bm_regs *)IOCFG_BM_BASE) +#define mtk_spm ((struct mtk_spm_regs *)SPM_BASE) +#define mtk_spmi_mst ((struct mtk_spmi_mst_reg *)SPMI_MST_BASE) + +struct cali { + unsigned int dly; + unsigned int pol; +}; + +enum { + SPMI_CK_NO_DLY = 0, + SPMI_CK_DLY_1T, +}; + +enum { + SPMI_CK_POL_NEG = 0, + SPMI_CK_POL_POS, +}; + +enum spmi_regs { + SPMI_OP_ST_CTRL, + SPMI_GRP_ID_EN, + SPMI_OP_ST_STA, + SPMI_MST_SAMPL, + SPMI_MST_REQ_EN, + SPMI_REC_CTRL, + SPMI_REC0, + SPMI_REC1, + SPMI_REC2, + SPMI_REC3, + SPMI_REC4, + SPMI_MST_DBG +}; + +/* MT6315 registers */ +enum { + MT6315_BASE = 0x0, + MT6315_READ_TEST = MT6315_BASE + 0x9, + MT6315_READ_TEST_1 = MT6315_BASE + 0xb, +}; + +#define MT6315_DEFAULT_VALUE_READ 0x15 + +extern int pmif_spmi_init(struct pmif *arb); +#endif /*__PMIF_SPMI_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif_sw.h b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h new file mode 100644 index 0000000000..fb4cbc967e --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/pmif_sw.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PMIF_SW_H__ +#define __PMIF_SW_H__ + +/* Read/write byte limitation, by project */ +/* hw bytecnt indicate when we set 0, it can send 1 byte; + * set 1, it can send 2 byte. + */ +#define PMIF_BYTECNT_MAX 1 + +/* macro for SWINF_FSM */ +#define SWINF_FSM_IDLE 0x00 +#define SWINF_FSM_REQ 0x02 +#define SWINF_FSM_WFDLE 0x04 +#define SWINF_FSM_WFVLDCLR 0x06 +#define SWINF_INIT_DONE 0x01 + +#define FREQ_METER_ABIST_AD_OSC_CK 37 +#define GET_SWINF_0_FSM(x) (((x) >> 1) & 0x7) + +struct pmif_mpu { + unsigned int rgn_slvid; + unsigned short rgn_s_addr; + unsigned short rgn_e_addr; + unsigned int rgn_domain_per; +}; + +enum { + PMIF_READ_US = 1000, + PMIF_WAIT_IDLE_US = 1000, +}; + +enum { + FREQ_260MHZ = 260, +}; + +/* calibation tolerance rate, unit: 0.1% */ +enum { + CAL_TOL_RATE = 40, + CAL_MAX_VAL = 0x7F, +}; + +extern int pmif_clk_init(void); +#endif /*__PMIF_SW_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/spmi.h b/src/soc/mediatek/mt8192/include/soc/spmi.h new file mode 100644 index 0000000000..0d44198f82 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spmi.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SPMI_H__ +#define __SPMI_H__ + +enum spmi_master { + SPMI_MASTER_0, + SPMI_MASTER_1, + SPMI_MASTER_2, + SPMI_MASTER_3, +}; + +enum spmi_slave { + SPMI_SLAVE_0, + SPMI_SLAVE_1, + SPMI_SLAVE_2, + SPMI_SLAVE_3, + SPMI_SLAVE_4, + SPMI_SLAVE_5, + SPMI_SLAVE_6, + SPMI_SLAVE_7, + SPMI_SLAVE_8, + SPMI_SLAVE_9, + SPMI_SLAVE_10, + SPMI_SLAVE_11, + SPMI_SLAVE_12, + SPMI_SLAVE_13, + SPMI_SLAVE_14, + SPMI_SLAVE_15, + SPMI_SLAVE_MAX, +}; + +enum slv_type { + BUCK_CPU, + BUCK_GPU, + SLV_TYPE_MAX, +}; + +enum slv_type_id { + BUCK_CPU_ID, + BUCK_GPU_ID, + SLV_TYPE_ID_MAX, +}; + +struct spmi_device { + u32 slvid; + enum slv_type type; + enum slv_type_id type_id; +}; +#endif /*__SPMI_H__*/ -- cgit v1.2.3