From 131f3435fcd0e8beb94eb4d132788e5303a7550a Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Tue, 23 Jun 2020 10:19:17 +0800 Subject: soc/mediatek/mt8192: Do memory pll init before calibration Memory PLL is used to provide the basic clock for dram controller and DDRPHY. PLL must be initialized as predefined way. First, enable PLL POWER and ISO, wait at least 30us, release ISO, then configure PLL frequency and enable PLL master switch. At last, enable control ability for SPM to switch between active and idle when system is switched between normal and low power mode. TEST=Confirm Memory PLL frequency is right by frequency meter Signed-off-by: Huayang Duan Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Frans Hendriks --- src/soc/mediatek/mt8192/include/soc/pll.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/mediatek/mt8192/include') diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 52bf3c2f38..cd1c01250c 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -241,6 +241,8 @@ check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200); check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300); check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc); +#define MPLL_CON1_FREQ 0x84200000 + enum { USBPLL_EN = 0x1 << 2, @@ -306,6 +308,12 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +DEFINE_BIT(MPLL_IOS_SEL, 2) +DEFINE_BIT(MPLL_EN_SEL, 11) +DEFINE_BIT(MPLL_PWR_SEL, 20) +DEFINE_BIT(MPLL_BY_ISO_DLY, 2) +DEFINE_BIT(MPLL_BY_PWR_DLY, 2) + DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12) -- cgit v1.2.3