From a6cd1bd6a89cb92bb0cc0a6cdae4d912644974de Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Tue, 18 Oct 2022 18:59:41 +0800 Subject: soc/mediatek: Unify PLL function names For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8188/pll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/mediatek/mt8188') diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c index e88c1926fe..a519fdd876 100644 --- a/src/soc/mediatek/mt8188/pll.c +++ b/src/soc/mediatek/mt8188/pll.c @@ -573,7 +573,7 @@ void mt_pll_init(void) * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING CONSTANTS! */ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* turn off unused clock in infra_ao */ write32(&mt8188_infracfg_ao->module_sw_cg_1_set, 0x00004000); @@ -633,9 +633,9 @@ void mt_pll_set_tvd_pll1_freq(u32 freq) udelay(PLL_EN_DELAY); } -void edp_mux_set_sel(u32 sel) +void mt_pll_edp_mux_set_sel(u32 sel) { - mux_set_sel(&muxes[TOP_EDP_SEL], sel); + pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel); } void mt_pll_set_usb_clock(void) -- cgit v1.2.3