From 08d2016e506153494eb053cd3a2db66f6f780d90 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Thu, 10 Feb 2022 17:00:17 +0800 Subject: soc/mediatek/mt8186: Lower SPI NOR speed to 52MHiz The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's HW design, which is capable of up to 52MHz. Therefore, lower the speed to univpll_d3_d8 (52MHz). BUG=b:218775654 TEST=emerge-corsola coreboot TEST=Boot time didn't increase significantly BRAHCH=none Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796 Tested-by: build bot (Jenkins) Reviewed-by: Rex-BC Chen Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8186/pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/mediatek/mt8186/pll.c') diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c index 572e7ec45b..9fe6a5147f 100644 --- a/src/soc/mediatek/mt8186/pll.c +++ b/src/soc/mediatek/mt8186/pll.c @@ -253,7 +253,7 @@ static const struct mux_sel mux_sels[] = { { .id = TOP_DSI_OCC_SEL, .sel = 1 }, /* 1: univpll_d3_d2 */ { .id = TOP_SPMI_MST_SEL, .sel = 2 }, /* 2: ulposc1_d4 */ /* CLK_CFG_13 */ - { .id = TOP_SPINOR_SEL, .sel = 5 }, /* 5: mainpll_d7_d2 */ + { .id = TOP_SPINOR_SEL, .sel = 3 }, /* 3: univpll_d3_d8 */ { .id = TOP_NNA_SEL, .sel = 14 }, /* 14: nnapll_ck */ { .id = TOP_NNA1_SEL, .sel = 14 }, /* 14: nnapll_ck */ { .id = TOP_NNA2_SEL, .sel = 15 }, /* 15: nna2pll_ck */ -- cgit v1.2.3