From 122b45be6e6cca0ded8c9df65cefe6043b4fcb88 Mon Sep 17 00:00:00 2001 From: Sen Chu Date: Tue, 18 Oct 2022 14:02:14 +0800 Subject: soc/mediatek/mt8186: Add support for PMIC MT6315 On MT8186T, the big cores are powered on by MT6315 via PMIF. This patch adds the following changes. - Add MT6315 settings. - Configure PMIC PMIF for MT6315. BUG=b:249436110 TEST=build pass. BRANCH=corsola Signed-off-by: Sen Chu Signed-off-by: Bo-Chen Chen Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620 Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8186/mt6315.c | 108 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) create mode 100644 src/soc/mediatek/mt8186/mt6315.c (limited to 'src/soc/mediatek/mt8186/mt6315.c') diff --git a/src/soc/mediatek/mt8186/mt6315.c b/src/soc/mediatek/mt8186/mt6315.c new file mode 100644 index 0000000000..1e6f0357b0 --- /dev/null +++ b/src/soc/mediatek/mt8186/mt6315.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6315 datasheet v1.3.pdf". + * The setting values are provided by MeidaTek designers. + */ + +static const struct mt6315_setting init_setting_cpu[] = { + /* remove protection */ + {0x3A9, 0x63, 0xFF, 0}, + {0x3A8, 0x15, 0xFF, 0}, + {0x3A0, 0x9C, 0xFF, 0}, + {0x39F, 0xEA, 0xFF, 0}, + {0x993, 0x47, 0xFF, 0}, + {0x992, 0x29, 0xFF, 0}, + {0x1418, 0x55, 0xFF, 0}, + {0x1417, 0x43, 0xFF, 0}, + {0x3A2, 0x2A, 0xFF, 0}, + {0x3A1, 0x7C, 0xFF, 0}, + /* init settings for mt6315 */ + {0x997, 0xF, 0x7F, 0}, + {0x999, 0xF0, 0xF0, 0}, + {0x9A0, 0x0, 0x1F, 0}, + {0x9A1, 0x0, 0x1F, 0}, + {0x9A2, 0x0, 0x1F, 0}, + {0x9A3, 0x0, 0x1F, 0}, + {0x1440, 0x0, 0xE, 0}, + {0x1487, 0x58, 0xFF, 0}, + {0x148B, 0x3, 0x7F, 0}, + {0x148C, 0x3, 0x7F, 0}, + {0x1507, 0x58, 0xFF, 0}, + {0x150B, 0x3, 0x7F, 0}, + {0x150C, 0x3, 0x7F, 0}, + {0x1587, 0x58, 0xFF, 0}, + {0x158B, 0x3, 0x7F, 0}, + {0x158C, 0x3, 0x7F, 0}, + {0x1607, 0x58, 0xFF, 0}, + {0x160B, 0x3, 0x7F, 0}, + {0x160C, 0x3, 0x7F, 0}, + {0x1687, 0x22, 0x76, 0}, + {0x1688, 0xF, 0x2F, 0}, + {0x1689, 0xA1, 0xE1, 0}, + {0x168A, 0x79, 0x7F, 0}, + {0x168B, 0x12, 0x3F, 0}, + {0x168D, 0xC, 0xC, 0}, + {0x168E, 0xD7, 0xFF, 0}, + {0x168F, 0x81, 0xFF, 0}, + {0x1690, 0x3, 0x3F, 0}, + {0x1691, 0x22, 0x76, 0}, + {0x1692, 0xF, 0x2F, 0}, + {0x1693, 0xA1, 0xE1, 0}, + {0x1694, 0x79, 0x7F, 0}, + {0x1695, 0x12, 0x3F, 0}, + {0x1697, 0xC, 0xC, 0}, + {0x1698, 0xD7, 0xFF, 0}, + {0x1699, 0x81, 0xFF, 0}, + {0x169A, 0x3, 0x3F, 0}, + {0x169B, 0x22, 0x76, 0}, + {0x169C, 0xF, 0x2F, 0}, + {0x169D, 0xA1, 0xE1, 0}, + {0x169E, 0x79, 0xFF, 0}, + {0x169F, 0x12, 0x3F, 0}, + {0x16A1, 0xC, 0xC, 0}, + {0x16A2, 0xD7, 0xFF, 0}, + {0x16A3, 0x81, 0xFF, 0}, + {0x16A4, 0x3, 0x3F, 0}, + {0x16A5, 0x22, 0x76, 0}, + {0x16A6, 0xF, 0x2F, 0}, + {0x16A7, 0xA1, 0xE1, 0}, + {0x16A8, 0x79, 0xFF, 0}, + {0x16A9, 0x12, 0x3F, 0}, + {0x16AB, 0xC, 0xC, 0}, + {0x16AC, 0xD7, 0xFF, 0}, + {0x16AD, 0x81, 0xFF, 0}, + {0x16AE, 0x3, 0x3F, 0}, + {0x16CE, 0x0, 0x8, 0}, + {0x13, 0x2, 0x2, 0}, + {0x15, 0x1F, 0x1F, 0}, + {0x22, 0x12, 0x12, 0}, + {0x8A, 0x6, 0xF, 0}, + {0x10B, 0x3, 0x3, 0}, + {0x38B, 0x4, 0xFF, 0}, + {0xA07, 0x0, 0x1, 0}, + {0xA1A, 0x1F, 0x1F, 0}, + {0x1457, 0x0, 0xFF, 0}, + /* add protection */ + {0x3A1, 0x0, 0xFF, 0}, + {0x3A2, 0x0, 0xFF, 0}, + {0x1417, 0x0, 0xFF, 0}, + {0x1418, 0x0, 0xFF, 0}, + {0x992, 0x0, 0xFF, 0}, + {0x993, 0x0, 0xFF, 0}, + {0x39F, 0x0, 0xFF, 0}, + {0x3A0, 0x0, 0xFF, 0}, + {0x3A8, 0x0, 0xFF, 0}, + {0x3A9, 0x0, 0xFF, 0}, +}; + +void mt6315_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting_cpu); i++) + mt6315_write_field(MT6315_CPU, + init_setting_cpu[i].addr, init_setting_cpu[i].val, + init_setting_cpu[i].mask, init_setting_cpu[i].shift); +} -- cgit v1.2.3