From f8eed65e4cc52b314a6ad31927cf0ecb3e3ea7ac Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Thu, 11 Nov 2021 15:50:42 +0800 Subject: soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMA 1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8186/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/mediatek/mt8186/Makefile.inc') diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 7a61bbf793..2107ab83e2 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c @@ -31,6 +32,7 @@ romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c ramstage-y += ../common/timer.c timer.c -- cgit v1.2.3