From 5a69491a01b6fe32a975aee557348acc84fc7a40 Mon Sep 17 00:00:00 2001 From: Jiaxin Yu Date: Thu, 25 Apr 2019 17:14:26 +0800 Subject: mediatek/mt8183: Init audio related clock Enable audio clock, intbus clock, infra clock and mtkaif 26m clock.Needed by audio playback in firmware. BUG=b:117254418 BRANCH=none TEST=Build pass and verified on kukui p1 board Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d Signed-off-by: Jiaxin Yu Reviewed-on: https://review.coreboot.org/c/coreboot/+/32458 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/pll.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/mediatek/mt8183') diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de7fb..8608b4ac10 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -356,4 +356,16 @@ void mt_pll_init(void) /* enable [14] dramc_pll104m_ck */ setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* enable audio clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); + + /* enable intbus clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); + + /* enable infra clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); + + /* enable mtkaif 26m clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } -- cgit v1.2.3