From 54f8b9ee7428068f0acb27d43d70d95c64b1a7ba Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidi.lin@mediatek.com>
Date: Wed, 6 Jan 2021 15:27:13 +0800
Subject: soc/mediatek: rtc: Use `bool` as return type

BUG=b:176307061
TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot
     boot to shell on Asurada

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8183/include/soc/rtc.h |  3 ++-
 src/soc/mediatek/mt8183/rtc.c             | 24 ++++++++++++------------
 2 files changed, 14 insertions(+), 13 deletions(-)

(limited to 'src/soc/mediatek/mt8183')

diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index f7c189f5ae..7ca054a940 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -5,6 +5,7 @@
 
 #include <soc/pmic_wrap_common.h>
 #include <soc/rtc_common.h>
+#include <stdbool.h>
 
 /* RTC registers */
 enum {
@@ -205,7 +206,7 @@ enum {
 /* external API */
 void rtc_bbpu_power_on(void);
 int rtc_init(int recover);
-int rtc_gpio_init(void);
+bool rtc_gpio_init(void);
 void rtc_boot(void);
 u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size);
 void mt6358_dcxo_disable_unused(void);
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index 41dc5c04af..e90aa9df6e 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -11,7 +11,7 @@
 #define RTC_GPIO_USER_MASK	  ((1 << 13) - (1 << 8))
 
 /* initialize rtc setting of using dcxo clock */
-static int rtc_enable_dcxo(void)
+static bool rtc_enable_dcxo(void)
 {
 	u16 bbpu, con, osc32con, sec;
 
@@ -22,7 +22,7 @@ static int rtc_enable_dcxo(void)
 	mdelay(1);
 	if (!rtc_writeif_unlock()) {
 		rtc_info("rtc_writeif_unlock() failed\n");
-		return 0;
+		return false;
 	}
 
 	rtc_read(RTC_OSC32CON, &osc32con);
@@ -32,7 +32,7 @@ static int rtc_enable_dcxo(void)
 		    | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
 	if (!rtc_xosc_write(osc32con)) {
 		rtc_info("rtc_xosc_write() failed\n");
-		return 0;
+		return false;
 	}
 
 	rtc_read(RTC_CON, &con);
@@ -40,11 +40,11 @@ static int rtc_enable_dcxo(void)
 	rtc_read(RTC_AL_SEC, &sec);
 	rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec);
 
-	return 1;
+	return true;
 }
 
 /* initialize rtc related gpio */
-int rtc_gpio_init(void)
+bool rtc_gpio_init(void)
 {
 	u16 con;
 
@@ -115,7 +115,7 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
 		rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
 		if (stopwatch_expired(&sw)) {
 			rtc_info("get frequency time out !!\n");
-			return 0;
+			return false;
 		}
 	} while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);
 
@@ -143,7 +143,7 @@ u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
 }
 
 /* low power detect setting */
-static int rtc_lpd_init(void)
+static bool rtc_lpd_init(void)
 {
 	u16 con, sec;
 
@@ -152,19 +152,19 @@ static int rtc_lpd_init(void)
 	sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
 	rtc_write(RTC_AL_SEC, sec);
 	if (!rtc_write_trigger())
-		return 0;
+		return false;
 
 	/* init XOSC32 to detect 32k clock stop */
 	rtc_read(RTC_CON, &con);
 	con |= RTC_CON_XOSC32_LPEN;
 	if (!rtc_lpen(con))
-		return 0;
+		return false;
 
 	/* init EOSC32 to detect rtc low power */
 	rtc_read(RTC_CON, &con);
 	con |= RTC_CON_EOSC32_LPEN;
 	if (!rtc_lpen(con))
-		return 0;
+		return false;
 
 	rtc_read(RTC_CON, &con);
 	con &= ~RTC_CON_XOSC32_LPEN;
@@ -176,9 +176,9 @@ static int rtc_lpd_init(void)
 	sec |= RTC_LPD_OPT_EOSC_LPD;
 	rtc_write(RTC_AL_SEC, sec);
 	if (!rtc_write_trigger())
-		return 0;
+		return false;
 
-	return 1;
+	return true;
 }
 
 static bool rtc_hw_init(void)
-- 
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