From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/spi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/mediatek/mt8183/spi.c') diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 7672db7993..c77d7ef7d3 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -127,10 +127,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | + SPI_CFG1_CS_IDLE_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { -- cgit v1.2.3