From 47095d5ec35b4cbff9d4660cfe9521ed17a0d1ed Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Tue, 27 Apr 2021 21:20:06 +0800 Subject: soc/mediatek: Move the common part of SPI drivers to common/ The SPI drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Cherry P0 Signed-off-by: Rex-BC Chen Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8183/spi.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'src/soc/mediatek/mt8183/spi.c') diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 87362dc33c..c172f377da 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -103,23 +103,6 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); } -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, - unsigned int tick_dly) -{ - write32(®s->spi_cfg0_reg, - ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | - ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - - write32(®s->spi_cfg2_reg, - ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | - ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - - clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); -} - const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_ctrlr, -- cgit v1.2.3