From eb5e47dd9467602d09a3f8e6e4cf5dd702bb0cc4 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Mon, 15 Apr 2019 15:29:26 +0800 Subject: mediatek/mt8183: update dcxo output buffer setting DCXO consists of core that generates clock and output buffers that provide clock to other peripheral components. This patch mainly eliminates the extra power consumption of output buffers. We only enable the buffer for SOC and disable unused buffers for power-saving. Also disable useless buffer power mode to guarantee the lowest power state. BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Signed-off-by: Weiyi Lu Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323 Reviewed-by: Julius Werner Reviewed-by: You-Cheng Syu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/rtc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek/mt8183/rtc.c') diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 5879088434..3bd3ab4921 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -274,9 +274,10 @@ static void dcxo_init(void) rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* Enable clock buffer XO_SOC */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); -- cgit v1.2.3