From b0ab41e0279e47d3bb09d6cddc803686859e6985 Mon Sep 17 00:00:00 2001 From: Yuchen Huang Date: Tue, 18 Aug 2020 16:29:29 +0800 Subject: soc/mediatek/mt8192: add rtc MT6359P driver Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor mt8173 and mt8183 code by extracting common API. Move rtc_read and rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via pmic wrapper, while mt8192 accesses it via pmif. Reference datasheet: Document No: RH-D-2018-0101. Signed-off-by: Yuchen Huang Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8183/rtc.c | 109 ++++-------------------------------------- 1 file changed, 8 insertions(+), 101 deletions(-) (limited to 'src/soc/mediatek/mt8183/rtc.c') diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 400412fffb..41dc5c04af 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -2,8 +2,8 @@ #include #include -#include #include +#include #include #include #include @@ -20,7 +20,7 @@ static int rtc_enable_dcxo(void) rtc_write_trigger(); mdelay(1); - if (!rtc_writeif_unlock()) { /* Unlock for reload */ + if (!rtc_writeif_unlock()) { rtc_info("rtc_writeif_unlock() failed\n"); return 0; } @@ -44,7 +44,7 @@ static int rtc_enable_dcxo(void) } /* initialize rtc related gpio */ -static int rtc_gpio_init(void) +int rtc_gpio_init(void) { u16 con; @@ -67,7 +67,7 @@ static int rtc_gpio_init(void) return rtc_write_trigger(); } -static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) { u16 bbpu, osc32con; u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; @@ -142,93 +142,6 @@ static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) return fqmtr_data; } -/* 32k clock calibration */ -static u16 rtc_eosc_cali(void) -{ - u16 middle, diff1, diff2, cksel; - u16 val = 0; - u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END; - - rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); - cksel &= ~PMIC_FQMTR_CKSEL_MASK; - /* select EOSC_32 as fixed clock */ - rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K); - rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); - rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel); - - while (left <= right) { - middle = (right + left) / 2; - if (middle == left) - break; - - /* select 26M as target clock */ - val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); - - if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) - break; - if (val > RTC_FQMTR_HIGH_BASE) - right = middle; - else - left = middle; - } - - if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) - return middle; - - val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if (val > RTC_FQMTR_LOW_BASE) - diff1 = val - RTC_FQMTR_LOW_BASE; - else - diff1 = RTC_FQMTR_LOW_BASE - val; - - val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if (val > RTC_FQMTR_LOW_BASE) - diff2 = val - RTC_FQMTR_LOW_BASE; - else - diff2 = RTC_FQMTR_LOW_BASE - val; - - if (diff1 < diff2) - return left; - else - return right; -} - -void rtc_osc_init(void) -{ - u16 osc32con; - - /* enable 32K export */ - rtc_gpio_init(); - - /* Calibrate eosc32 for powerdown clock */ - rtc_read(RTC_OSC32CON, &osc32con); - osc32con &= ~RTC_XOSCCALI_MASK; - osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK; - rtc_xosc_write(osc32con); - rtc_info("EOSC32 cali val = 0x%x\n", osc32con); -} - -/* enable lpd subroutine */ -static int rtc_lpen(u16 con) -{ - con &= ~RTC_CON_LPRST; - rtc_write(RTC_CON, con); - if (!rtc_write_trigger()) - return 0; - - con |= RTC_CON_LPRST; - rtc_write(RTC_CON, con); - if (!rtc_write_trigger()) - return 0; - - con &= ~RTC_CON_LPRST; - rtc_write(RTC_CON, con); - if (!rtc_write_trigger()) - return 0; - - return 1; -} - /* low power detect setting */ static int rtc_lpd_init(void) { @@ -291,16 +204,8 @@ static bool rtc_hw_init(void) return true; } -/* write powerkeys to enable rtc functions */ -static int rtc_powerkey_init(void) -{ - rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); - rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); - return rtc_write_trigger(); -} - /* rtc init check */ -int rtc_init(u8 recover) +int rtc_init(int recover) { int ret; @@ -320,6 +225,7 @@ int rtc_init(u8 recover) rtc_osc_init(); + /* In recovery mode, we need 20ms delay for register setting. */ if (recover) mdelay(20); @@ -343,7 +249,8 @@ int rtc_init(u8 recover) goto err; } - /* After lpd init, powerkeys need to be written again to enable + /* + * After lpd init, powerkeys need to be written again to enable * low power detect function. */ if (!rtc_powerkey_init()) { -- cgit v1.2.3