From e621d8f11a2bdad4920cbb7c4293fdfd98adf4bd Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Tue, 19 Mar 2019 13:39:12 +0800 Subject: mediatek/mt8183: Add infra group DCM setting Add infra group DCM (Dynamic Clock Management) settings, which slows down OR gate clocks while hardware is in idle state. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I4741dfb7b984deb92171f370e5fb2593829d74c2 Signed-off-by: Weiyi Lu Reviewed-on: https://review.coreboot.org/c/coreboot/+/31977 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: You-Cheng Syu --- src/soc/mediatek/mt8183/pll.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/mediatek/mt8183/pll.c') diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 07ce6603f6..5368077318 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -344,6 +344,12 @@ void mt_pll_init(void) /* enable infrasys DCM */ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, + DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON); + setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); + clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); + clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl, + DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON); /* enable [11] for change i2c module source clock to TOPCKGEN */ setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); -- cgit v1.2.3