From cea735cf127e090fbb5fa588bd5d7bd3c959e49f Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Tue, 24 Sep 2019 14:07:11 +0800 Subject: soc/mediatek/mt8183: Run calibration with multiple frequencies for DVFS switch The patch adds config MT8183_DRAM_DVFS to enable DRAM calibration with multiple frequencies to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/35555 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/include/soc/dramc_register.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/mediatek/mt8183/include') diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index 61019b3110..b3ee6af4c7 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -288,7 +288,7 @@ struct dramc_ao_regs { uint32_t rsvd_10[46]; struct dramc_ao_regs_rk rk[3]; uint32_t rsvd_16[64]; - struct { + struct dramc_ao_regs_shu { uint32_t rsvd0[64]; uint32_t actim[7]; uint32_t actim_xrt; -- cgit v1.2.3