From c2ef1029fabfccbdd3e86c5f659f83109313c9f9 Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Wed, 26 Sep 2018 14:24:02 +0800 Subject: mediatek/mt8183: Add EMI init for DDR driver init Add EMI config to initialize memory. BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Signed-off-by: Huayang Duan Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea Reviewed-on: https://review.coreboot.org/28835 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- .../mt8183/include/soc/dramc_common_mt8183.h | 56 +++++++++ src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 135 +++++++++++++++++++++ src/soc/mediatek/mt8183/include/soc/emi.h | 22 +++- 3 files changed, 212 insertions(+), 1 deletion(-) create mode 100644 src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h create mode 100644 src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h (limited to 'src/soc/mediatek/mt8183/include') diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h new file mode 100644 index 0000000000..e699e80f8b --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRAMC_COMMON_MT8183_H_ +#define _DRAMC_COMMON_MT8183_H_ + +#define DRAM_DFS_SHUFFLE_MAX 3 + +enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX +}; + +enum { + RANK_0 = 0, + RANK_1, + RANK_MAX +}; + +enum dram_odt_type { + ODT_OFF = 0, + ODT_ON +}; + +enum { + DQ_DATA_WIDTH = 16, + DQS_BIT_NUMBER = 8, + DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER) +}; + +/* + * Internal CBT mode enum + * 1. Calibration flow uses vGet_Dram_CBT_Mode to + * differentiate between mixed vs non-mixed LP4 + * 2. Declared as dram_cbt_mode[RANK_MAX] internally to + * store each rank's CBT mode type + */ +enum { + CBT_NORMAL_MODE = 0, + CBT_BYTE_MODE1 +}; + +#endif /* _DRAMC_COMMON_MT8183_H_ */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h new file mode 100644 index 0000000000..e24bd6c8e8 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRAMC_PI_API_MT8183_H +#define _DRAMC_PI_API_MT8183_H + +#include +#include +#include + +#define dramc_show(_x_...) printk(BIOS_INFO, _x_) +#if IS_ENABLED(CONFIG_DEBUG_DRAM) +#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) +#else +#define dramc_dbg(_x_...) +#endif + +#define ENABLE 1 +#define DISABLE 0 + +#define DATLAT_TAP_NUMBER 32 + +#define MAX_CMP_CPT_WAIT_LOOP 10000 +#define TIME_OUT_CNT 100 + +#define DRAMC_BROADCAST_ON 0x1f +#define DRAMC_BROADCAST_OFF 0x0 +#define MAX_BACKUP_REG_CNT 32 + +enum dram_te_op { + TE_OP_WRITE_READ_CHECK = 0, + TE_OP_READ_CHECK +}; + +enum { + DBI_OFF = 0, + DBI_ON +}; + +enum { + FSP_0 = 0, + FSP_1, + FSP_MAX +}; + +enum { + TX_DQ_DQS_MOVE_DQ_ONLY = 0, + TX_DQ_DQS_MOVE_DQM_ONLY, + TX_DQ_DQS_MOVE_DQ_DQM +}; + +enum { + MAX_CA_FINE_TUNE_DELAY = 63, + MAX_CS_FINE_TUNE_DELAY = 63, + MAX_CLK_FINE_TUNE_DELAY = 31, + CATRAINING_NUM = 6, + PASS_RANGE_NA = 0x7fff +}; + +enum { + GATING_OFF = 0, + GATING_ON = 1 +}; + +enum { + CKE_FIXOFF = 0, + CKE_FIXON, + CKE_DYNAMIC +}; + +enum { + GATING_PATTERN_NUM = 0x23, + GATING_GOLDEND_DQSCNT = 0x4646 +}; + +enum { + IMPCAL_STAGE_DRVP = 0x1, + IMPCAL_STAGE_DRVN, + IMPCAL_STAGE_TRACKING +}; + +enum { + DQS_GW_COARSE_STEP = 1, + DQS_GW_FINE_START = 0, + DQS_GW_FINE_END = 32, + DQS_GW_FINE_STEP = 4, + DQS_GW_FREQ_DIV = 4, + RX_DQS_CTL_LOOP = 8, + RX_DLY_DQSIENSTB_LOOP = 32 +}; + +enum { + SAVE_VALUE, + RESTORE_VALUE +}; + +enum { + DQ_DIV_SHIFT = 3, + DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, + OEN_SHIFT = 16, + + DQS_DELAY_2T = 3, + DQS_DELAY_0P5T = 4, + DQS_DELAY = ((DQS_DELAY_2T << DQ_DIV_SHIFT) + DQS_DELAY_0P5T) << 5, + + DQS_OEN_DELAY_2T = 3, + DQS_OEN_DELAY_0P5T = 1, + + SELPH_DQS0 = (DQS_DELAY_2T << 0) | (DQS_DELAY_2T << 4) | + (DQS_DELAY_2T << 8) | (DQS_DELAY_2T << 12) | + (DQS_OEN_DELAY_2T << 16) | (DQS_OEN_DELAY_2T << 20) | + (DQS_OEN_DELAY_2T << 24) | (DQS_OEN_DELAY_2T << 28), + + SELPH_DQS1 = (DQS_DELAY_0P5T << 0) | (DQS_DELAY_0P5T << 4) | + (DQS_DELAY_0P5T << 8) | (DQS_DELAY_0P5T << 12) | + (DQS_OEN_DELAY_0P5T << 16) | (DQS_OEN_DELAY_0P5T << 20) | + (DQS_OEN_DELAY_0P5T << 24) | (DQS_OEN_DELAY_0P5T << 28) +}; + +void dramc_get_rank_size(u64 *dram_rank_size); +void dramc_set_broadcast(u32 onoff); +u32 dramc_get_broadcast(void); +#endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index edc27a8c99..c3c8e81cfa 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -18,7 +18,27 @@ #include #include +#include +struct sdram_params { + u32 impedance[2][4]; + u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; + u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; + s8 clk_delay; + s8 dqs_delay[CHANNEL_MAX]; + u32 emi_cona_val; + u32 emi_conh_val; + u32 emi_conf_val; + u32 chn_emi_cona_val[CHANNEL_MAX]; + u32 cbt_mode_extern; + u16 delay_cell_unit; +}; + +int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); +const struct sdram_params *get_sdram_config(void); +void mt_set_emi(const struct sdram_params *params); +void mt_mem_init(const struct sdram_params *params); -#endif +#endif /* SOC_MEDIATEK_MT8183_EMI_H */ -- cgit v1.2.3