From 9400f84d3111ee888ac1a2b2e1fc942873e0d67a Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Mon, 19 Aug 2019 16:40:01 +0800 Subject: mediatek/mt8183: Use different DRAM frequencies for eMCP DDR Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps) while those with discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for eMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test passes on Kukui Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/soc/mediatek/mt8183/include') diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index e699e80f8b..ef6eaf162c 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -16,7 +16,12 @@ #ifndef _DRAMC_COMMON_MT8183_H_ #define _DRAMC_COMMON_MT8183_H_ -#define DRAM_DFS_SHUFFLE_MAX 3 +enum { + DRAM_DFS_SHUFFLE_1 = 0, + DRAM_DFS_SHUFFLE_2, + DRAM_DFS_SHUFFLE_3, + DRAM_DFS_SHUFFLE_MAX +}; enum { CHANNEL_A = 0, -- cgit v1.2.3