From 5ff588dbc10bbf69f140cebf3a584f1ed563b1c5 Mon Sep 17 00:00:00 2001 From: Shaoming Chen Date: Fri, 4 Dec 2020 17:00:56 +0800 Subject: soc/mediatek/mt8183: Support byte mode and single rank DDR 1. Add emi setting to support byte mode and single rank ddr sample 2. Modify initial setting for DDR with different architecture BUG=b:165768895 BRANCH=kukui TEST=DDR boot up correctly on Kukui Signed-off-by: Shaoming Chen Change-Id: Id2845b2b60e2c447486ee25259dc6a05a0bb619b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48300 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h | 7 +++++++ src/soc/mediatek/mt8183/include/soc/dramc_param.h | 6 +++++- src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h | 13 +++++++------ src/soc/mediatek/mt8183/include/soc/emi.h | 1 + 4 files changed, 20 insertions(+), 7 deletions(-) (limited to 'src/soc/mediatek/mt8183/include') diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index c630b5aa90..9ab889b8e1 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -47,6 +47,13 @@ enum { CBT_BYTE_MODE1 }; +enum { + CBT_R0_R1_NORMAL = 0, /* Normal mode */ + CBT_R0_R1_BYTE, /* Byte mode */ + CBT_R0_NORMAL_R1_BYTE, /* Mixed mode R0: Normal R1: Byte */ + CBT_R0_BYTE_R1_NORMAL /* Mixed mode R0: Byte R1: Normal */ +}; + enum { FSP_0 = 0, FSP_1, diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index f925162e4a..3758547d13 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -10,7 +10,7 @@ enum { DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b, - DRAMC_PARAM_HEADER_VERSION = 4, + DRAMC_PARAM_HEADER_VERSION = 5, }; enum DRAMC_PARAM_STATUS_CODES { @@ -38,9 +38,13 @@ enum DRAMC_PARAM_FLAGS { }; enum DRAMC_PARAM_GEOMETRY_TYPE { + DDR_TYPE_2CH_1RK_4GB_4, DDR_TYPE_2CH_2RK_4GB_2_2, DDR_TYPE_2CH_2RK_6GB_3_3, DDR_TYPE_2CH_2RK_8GB_4_4, + DDR_TYPE_2CH_RK0_RK1_BYTE_8GB_4_4, + DDR_TYPE_2CH_RK0_NORMAL_RK1_BYTE_8GB_4_4, + DDR_TYPE_2CH_RK0_BYTE_RK1_NORMAL_8GB_4_4, }; struct dramc_param_header { diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index a0937d01c6..b1a0c74f14 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -97,7 +97,7 @@ enum { }; void dramc_get_rank_size(u64 *dram_rank_size); -void dramc_runtime_config(void); +void dramc_runtime_config(u32 rk_num); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); u8 get_freq_fsq(u8 freq_group); @@ -107,18 +107,19 @@ void dramc_sw_impedance_save_reg(u8 freq_group, const struct dram_impedance *impedance); void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option, struct dram_impedance *impedance); -void dramc_apply_config_before_calibration(u8 freq_group); -void dramc_apply_config_after_calibration(const struct mr_value *mr); +void dramc_apply_config_before_calibration(u8 freq_group, u32 cbt_mode); +void dramc_apply_config_after_calibration(const struct mr_value *mr, u32 rk_num); int dramc_calibrate_all_channels(const struct sdram_params *pams, - u8 freq_group, struct mr_value *mr); + u8 freq_group, struct mr_value *mr, bool run_dvfs); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(u8 chn, bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); u32 get_shu_freq(u8 shu); -void dramc_hw_dqsosc(u8 chn); +void dramc_hw_dqsosc(u8 chn, u32 rk_num); void dramc_dqs_precalculation_preset(void); -void get_dram_info_after_cal(u8 *density); +void get_dram_info_after_cal(u8 *density, u32 rk_num); void set_mrr_pinmux_mapping(void); void dramc_cke_fix_onoff(enum cke_type option, u8 chn); +void cbt_mrr_pinmux_mapping(void); #endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 6931d5bb81..16f0b2e8f5 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -15,6 +15,7 @@ enum DRAMC_PARAM_SOURCE { struct sdram_params { u16 source; /* DRAMC_PARAM_SOURCE */ u16 frequency; + u32 rank_num; u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */ u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; -- cgit v1.2.3