From a6cd1bd6a89cb92bb0cc0a6cdae4d912644974de Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Tue, 18 Oct 2022 18:59:41 +0800 Subject: soc/mediatek: Unify PLL function names For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8173/pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek/mt8173') diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index 7133fde400..bbbb1f325c 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -347,7 +347,7 @@ void mt_pll_init(void) * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING CONSTANTS! *************/ for (i = 0; i < ARRAY_SIZE(mux_sels); i++) - mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); + pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* enable scpsys clock off control */ write32(&mtk_topckgen->clk_scp_cfg_0, @@ -445,5 +445,5 @@ void mt_mem_pll_config_post(void) void mt_mem_pll_mux(void) { /* CLK_CFG_0 */ - mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */ + pll_mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */ } -- cgit v1.2.3