From 00324b20e102f9f0f040077b584da12ba3fd699c Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Wed, 27 Jul 2022 16:12:12 +0800 Subject: soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay setting MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8173/include/soc/spi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/mediatek/mt8173') diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index b267aa0d92..4a81eae5db 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -8,6 +8,7 @@ #define SPI_BUS_NUMBER 1 #define GET_SCK_REG(x) x->spi_cfg0_reg +#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0) DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8) @@ -17,6 +18,6 @@ DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 24) DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 28, 16) -DEFINE_BITFIELD(SPI_CFG1_TICK_DLY, 31, 29) +DEFINE_BITFIELD(SPI_TICK_DLY, 31, 29) #endif -- cgit v1.2.3