From b17e805dbf6a767c5dfb0deece4cc504ad7367f0 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Mon, 28 Dec 2020 21:59:11 +0800 Subject: soc/mediatek/mt8192: Move flash_controller.c to common/ The flash controller driver can be shared among mt8173 and mt819x. TEST=boot to kernel on Asurada boot to kernel on Hana (w/o BL31) Change-Id: I4e5213563189336496122a0f2d8077b3e5245314 Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/48972 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- .../mediatek/mt8173/include/soc/flash_controller.h | 78 ---------------------- src/soc/mediatek/mt8173/include/soc/symbols.h | 1 + 2 files changed, 1 insertion(+), 78 deletions(-) delete mode 100644 src/soc/mediatek/mt8173/include/soc/flash_controller.h (limited to 'src/soc/mediatek/mt8173/include') diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h deleted file mode 100644 index 6ac8da3471..0000000000 --- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ -#define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ - -#include -#include -#include - -enum { - SFLASH_POLLINGREG_US = 500000, - SFLASH_WRBUF_SIZE = 128, - SFLASHNAME_LENGTH = 16, - SFLASH_WRITE_IN_PROGRESS = 1, - SFLASH_COMMAND_ENABLE = 0x30, - SFLASH_DMA_ALIGN = 0x10, - - /* NOR flash controller commands */ - SFLASH_RD_TRIGGER = 1 << 0, - SFLASH_READSTATUS = 1 << 1, - SFLASH_PRG_CMD = 1 << 2, - SFLASH_WR_TRIGGER = 1 << 4, - SFLASH_WRITESTATUS = 1 << 5, - SFLASH_AUTOINC = 1 << 7, - /* NOR flash commands */ - SFLASH_OP_WREN = 0x6, - SECTOR_ERASE_CMD = 0x20, - SFLASH_UNPROTECTED = 0x0, - /* DMA commands */ - SFLASH_DMA_TRIGGER = 1 << 0, - SFLASH_DMA_SW_RESET = 1 << 1, - SFLASH_DMA_WDLE_EN = 1 << 2 -}; - -/* register Offset */ -struct mt8173_nor_regs { - u32 cmd; - u32 cnt; - u32 rdsr; - u32 rdata; - u32 radr[3]; - u32 wdata; - u32 prgdata[6]; - u32 shreg[10]; - u32 cfg[2]; - u32 shreg10; - u32 status[5]; - u32 timing; - u32 flash_cfg; - u32 reserved2[3]; - u32 sf_time; - u32 reserved3; - u32 diff_addr; - u32 del_sel[2]; - u32 intrstus; - u32 intren; - u32 pp_ctl; - u32 cfg3; - u32 chksum_ctl; - u32 chksum; - u32 aaicmd; - u32 wrprot; - u32 radr3; - u32 read_dual; - u32 delsel[3]; - u32 reserved[397]; - u32 cfg1_bri[2]; - u32 fdma_ctl; - u32 fdma_fadr; - u32 fdma_dadr; - u32 fdma_end_dadr; -}; -check_member(mt8173_nor_regs, fdma_end_dadr, 0x724); -static struct mt8173_nor_regs *const mt8173_nor = (void *)SFLASH_REG_BASE; - -int mtk_spi_flash_probe(const struct spi_slave *spi, struct spi_flash *flash); - -#endif /* __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/symbols.h b/src/soc/mediatek/mt8173/include/soc/symbols.h index 1cf6dde0c9..ae5d998c6b 100644 --- a/src/soc/mediatek/mt8173/include/soc/symbols.h +++ b/src/soc/mediatek/mt8173/include/soc/symbols.h @@ -2,6 +2,7 @@ #ifndef __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ #define __SOC_MEDIATEK_MT8173_DRAM_DMA_H__ +#include DECLARE_REGION(dram_dma) -- cgit v1.2.3