From a3f7fe8219654aa90ab2ea9458267e5136a03a01 Mon Sep 17 00:00:00 2001 From: mtk05962 Date: Fri, 16 Oct 2015 13:42:49 +0800 Subject: mt8173: add SPI NOR support BRANCH=none BUG=none TEST=boot oak to kernel on rev1 Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c Signed-off-by: Patrick Georgi Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18 Original-Signed-off-by: mtk05962 Original-Reviewed-on: https://chromium-review.googlesource.com/292693 Original-Commit-Ready: Yidi Lin Original-Tested-by: Yidi Lin Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/13102 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../mediatek/mt8173/include/soc/flash_controller.h | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 src/soc/mediatek/mt8173/include/soc/flash_controller.h (limited to 'src/soc/mediatek/mt8173/include') diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h new file mode 100644 index 0000000000..2527d6be6a --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/flash_controller.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ +#define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ + +#include +#include +#include +#include + +enum { + SFLASH_POLLINGREG_US = 500000, + SFLASH_WRBUF_SIZE = 128, + SFLASHNAME_LENGTH = 16, + SFLASH_WRITE_IN_PROGRESS = 1, + SFLASH_COMMAND_ENABLE = 0x30, + + /* NOR flash controller commands */ + SFLASH_RD_TRIGGER = 1 << 0, + SFLASH_READSTATUS = 1 << 1, + SFLASH_PRG_CMD = 1 << 2, + SFLASH_WR_TRIGGER = 1 << 4, + SFLASH_WRITESTATUS = 1 << 5, + SFLASH_AUTOINC = 1 << 7, + /* NOR flash commands */ + SFLASH_OP_WREN = 0x6, + SECTOR_ERASE_CMD = 0x20, + SFLASH_UNPROTECTED = 0x0 +}; + +/* register Offset */ +struct mt8173_nor_regs { + u32 cmd; + u32 cnt; + u32 rdsr; + u32 rdata; + u32 radr[3]; + u32 wdata; + u32 prgdata[6]; + u32 shreg[10]; + u32 cfg[2]; + u32 shreg10; + u32 status[5]; + u32 timing; + u32 flash_cfg; + u32 reserved2[3]; + u32 sf_time; + u32 reserved3; + u32 diff_addr; + u32 del_sel[2]; + u32 intrstus; + u32 intren; + u32 pp_ctl; + u32 cfg3; + u32 chksum_ctl; + u32 chksum; + u32 aaicmd; + u32 wrprot; + u32 radr3; + u32 read_dual; + u32 delsel[3]; +}; +check_member(mt8173_nor_regs, delsel[2], 0xD8); +static struct mt8173_nor_regs * const mt8173_nor = (void *)SFLASH_REG_BASE; + +struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi); +#endif /* __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__ */ -- cgit v1.2.3