From 5d7c38ffa93b9713796bbccbf9c29cbacc1732d6 Mon Sep 17 00:00:00 2001 From: Koro Chen Date: Tue, 4 Aug 2015 16:16:46 +0800 Subject: mediatek/mt8173: add APLL clock setting Add a new function mt_pll_set_aud_div() to set APLL for audio I2S. The function is called by mainboard's configure_audio(). BRANCH=chromeos-2015.07 BUG=chrome-os-partner:41507 TEST=build and verified pass on oak board Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75 Signed-off-by: Patrick Georgi Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6 Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f Original-Signed-off-by: Koro Chen Original-Reviewed-on: https://chromium-review.googlesource.com/297225 Original-Commit-Ready: Yidi Lin Original-Tested-by: Yidi Lin Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/13090 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/mediatek/mt8173/include/soc/pll.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/mediatek/mt8173/include') diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index d41e2ae518..aa9c8bbca9 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -283,5 +283,6 @@ enum { void mt_pll_post_init(void); void mt_pll_init(void); +void mt_pll_set_aud_div(u32 rate); #endif /* SOC_MEDIATEK_MT8173_PLL_H */ -- cgit v1.2.3