From 026be3d76f3934eb901485acd98e0d84f137068f Mon Sep 17 00:00:00 2001
From: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Date: Wed, 24 Apr 2019 11:11:52 +0800
Subject: mediatek: Add SPI tick_dly setting

Add spi tick_dly setting for high-speed spi xfer.

BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot

Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/soc/mediatek/mt8173/include/soc/spi.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/soc/mediatek/mt8173/include')

diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h
index aaef3aa25c..58bf517f9d 100644
--- a/src/soc/mediatek/mt8173/include/soc/spi.h
+++ b/src/soc/mediatek/mt8173/include/soc/spi.h
@@ -43,4 +43,9 @@ enum {
 	SPI_CFG0_CS_SETUP_SHIFT = 24,
 };
 
+enum {
+	SPI_CFG1_TICK_DLY_SHIFT = 30,
+	SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT,
+};
+
 #endif
-- 
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