From 55009af42c39f413c49503670ce9bc2858974962 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 2 Dec 2019 22:03:27 -0800 Subject: Change all clrsetbits_leXX() to clrsetbitsXX() This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8173/gpio_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek/mt8173/gpio_init.c') diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index e991a5f75d..c701034a52 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -25,14 +25,14 @@ */ static void set_gpi_from_mipi(void) { - setbits_le32(&mt8173_mipi->mipi_rx_ana4c, + setbits32(&mt8173_mipi->mipi_rx_ana4c, 1 << 0 | /* RG_MIPI_GPI0_IES GPI47 */ 1 << 6 | /* RG_MIPI_GPI1_IES GPI48 */ 1 << 12 | /* RG_MIPI_GPI2_IES GPI49 */ 1 << 18 | /* RG_MIPI_GPI3_IES GPI50 */ 1 << 24); /* RF_MIPI_GPI4_IES GPI51 */ - setbits_le32(&mt8173_mipi->mipi_rx_ana50, + setbits32(&mt8173_mipi->mipi_rx_ana50, 1 << 0 | /* RG_MIPI_GPI5_IES GPI52 */ 1 << 6 | /* RG_MIPI_GPI6_IES GPI53 */ 1 << 12 | /* RG_MIPI_GPI7_IES GPI54 */ -- cgit v1.2.3