From 71d227b1085b5f54b11a6fcfa9419597ee5c9f56 Mon Sep 17 00:00:00 2001 From: Tristan Shieh Date: Mon, 9 Jul 2018 18:59:32 +0800 Subject: mediatek: Share GPIO code among similar SOCs Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/mediatek/mt8173/gpio.c | 153 ++++------------------------------------- 1 file changed, 15 insertions(+), 138 deletions(-) (limited to 'src/soc/mediatek/mt8173/gpio.c') diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index c5ca08b923..518df851f1 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -14,80 +14,38 @@ */ #include #include -#include #include #include -#include -#include enum { - MAX_8173_GPIO = 134, - MAX_GPIO_REG_BITS = 16, - MAX_GPIO_MODE_PER_REG = 5, - GPIO_MODE_BITS = 3, + MAX_GPIO_NUMBER = 134, MAX_EINT_REG_BITS = 32, }; -enum { - GPIO_DIRECTION_IN = 0, - GPIO_DIRECTION_OUT = 1, -}; - -enum { - GPIO_MODE = 0, -}; - -static void pos_bit_calc(u32 pin, u32 *pos, u32 *bit) +static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit) { - *pos = pin / MAX_GPIO_REG_BITS; - *bit = pin % MAX_GPIO_REG_BITS; + *pos = gpio.id / MAX_GPIO_REG_BITS; + *bit = gpio.id % MAX_GPIO_REG_BITS; } -static void pos_bit_calc_for_mode(u32 pin, u32 *pos, u32 *bit) +static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit) { - *pos = pin / MAX_GPIO_MODE_PER_REG; - *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; -} - -static void pos_bit_calc_for_eint(u32 pin, u32 *pos, u32 *bit) -{ - *pos = pin / MAX_EINT_REG_BITS; - *bit = pin % MAX_EINT_REG_BITS; -} - -static s32 gpio_set_dir(u32 pin, u32 dir) -{ - u32 pos; - u32 bit; - u16 *reg; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - if (dir == GPIO_DIRECTION_IN) - reg = &mt8173_gpio->dir[pos].rst; - else - reg = &mt8173_gpio->dir[pos].set; - - write16(reg, 1L << bit); - - return 0; + *pos = gpio.id / MAX_EINT_REG_BITS; + *bit = gpio.id % MAX_EINT_REG_BITS; } -void gpio_set_pull(gpio_t pin, enum pull_enable enable, +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select) { u32 pos; u32 bit; - u16 *en_reg, *sel_reg; + u32 *en_reg, *sel_reg; + u32 pin = gpio.id; - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); + pos_bit_calc(gpio, &pos, &bit); if (enable == GPIO_PULL_DISABLE) { - en_reg = &mt8173_gpio->pullen[pos].rst; + en_reg = &mtk_gpio->pullen[pos].rst; } else { /* These pins' pulls can't be set through GPIO controller. */ assert(pin < 22 || pin > 27); @@ -97,100 +55,21 @@ void gpio_set_pull(gpio_t pin, enum pull_enable enable, assert(pin < 100 || pin > 105); assert(pin < 119 || pin > 124); - en_reg = &mt8173_gpio->pullen[pos].set; + en_reg = &mtk_gpio->pullen[pos].set; sel_reg = (select == GPIO_PULL_DOWN) ? - (&mt8173_gpio->pullsel[pos].rst) : - (&mt8173_gpio->pullsel[pos].set); + (&mtk_gpio->pullsel[pos].rst) : + (&mtk_gpio->pullsel[pos].set); write16(sel_reg, 1L << bit); } write16(en_reg, 1L << bit); } -int gpio_get(gpio_t pin) -{ - u32 pos; - u32 bit; - u16 *reg; - s32 data; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - reg = &mt8173_gpio->din[pos].val; - data = read32(reg); - - return (data & (1L << bit)) ? 1 : 0; -} - -void gpio_set(gpio_t pin, int output) -{ - u32 pos; - u32 bit; - u16 *reg; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - if (output == 0) - reg = &mt8173_gpio->dout[pos].rst; - else - reg = &mt8173_gpio->dout[pos].set; - write16(reg, 1L << bit); -} - -void gpio_set_mode(gpio_t pin, int mode) -{ - u32 pos; - u32 bit; - u32 mask = (1L << GPIO_MODE_BITS) - 1; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc_for_mode(pin, &pos, &bit); - - clrsetbits_le32(&mt8173_gpio->mode[pos].val, - mask << bit, mode << bit); -} - -void gpio_input_pulldown(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_input_pullup(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_input(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_output(gpio_t gpio, int value) -{ - gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); - gpio_set(gpio, value); - gpio_set_dir(gpio, GPIO_DIRECTION_OUT); - gpio_set_mode(gpio, GPIO_MODE); -} - int gpio_eint_poll(gpio_t gpio) { u32 pos; u32 bit; u32 status; - assert(gpio <= MAX_8173_GPIO); - pos_bit_calc_for_eint(gpio, &pos, &bit); status = (read32(&mt8173_eint->sta.regs[pos]) >> bit) & 0x1; @@ -206,8 +85,6 @@ void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type) u32 pos; u32 bit, mask; - assert(gpio <= MAX_8173_GPIO); - pos_bit_calc_for_eint(gpio, &pos, &bit); mask = 1 << bit; -- cgit v1.2.3