From 4c8d4872a56ea99feb3397619927db360b2f6339 Mon Sep 17 00:00:00 2001 From: Tristan Shieh Date: Wed, 6 Jun 2018 13:35:12 +0800 Subject: mediatek: Refactor to sharing code among similar SOCs This patch refactor cbmem and timer code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232 Signed-off-by: Tristan Shieh Reviewed-on: https://review.coreboot.org/26881 Reviewed-by: Patrick Georgi Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8173/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/mediatek/mt8173/Makefile.inc') diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index fecd7f165e..3aa463a928 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -20,6 +20,7 @@ bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-y += i2c.c bootblock-y += pll.c bootblock-y += spi.c +bootblock-y += common_timer.c bootblock-y += timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) @@ -37,6 +38,7 @@ verstage-y += spi.c verstage-$(CONFIG_DRIVERS_UART) += uart.c +verstage-y += common_timer.c verstage-y += timer.c verstage-y += wdt.c verstage-$(CONFIG_SPI_FLASH) += flash_controller.c @@ -46,6 +48,7 @@ verstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += flash_controller.c romstage-y += pll.c +romstage-y += common_timer.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c @@ -64,6 +67,7 @@ ramstage-y += cbmem.c emi.c ramstage-y += spi.c ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c ramstage-y += soc.c mtcmos.c +ramstage-y += common_timer.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += pmic_wrap.c mt6391.c i2c.c -- cgit v1.2.3