From 17180af69a95ad5823c501737d0ba2a0e849b4df Mon Sep 17 00:00:00 2001 From: Tristan Shieh Date: Mon, 2 Jul 2018 17:20:13 +0800 Subject: mediatek: Share PLL code among similar SOCs Refactor PLL code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Signed-off-by: Tristan Shieh Reviewed-on: https://review.coreboot.org/27305 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8173/Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/mediatek/mt8173/Makefile.inc') diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index d66183250e..003feabece 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -18,7 +18,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) bootblock-y += bootblock.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c bootblock-y += i2c.c -bootblock-y += pll.c +bootblock-y += ../common/pll.c pll.c bootblock-y += spi.c bootblock-y += ../common/timer.c bootblock-y += timer.c @@ -47,7 +47,7 @@ verstage-y += gpio.c ################################################################################ romstage-$(CONFIG_SPI_FLASH) += flash_controller.c -romstage-y += pll.c +romstage-y += ../common/pll.c pll.c romstage-y += ../common/timer.c romstage-y += timer.c @@ -75,7 +75,7 @@ ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += gpio.c ramstage-y += ../common/wdt.c -ramstage-y += pll.c +ramstage-y += ../common/pll.c pll.c ramstage-y += rtc.c ramstage-y += usb.c -- cgit v1.2.3