From af3f8298d62832d1bb2bee4ef08097052e07c1a7 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Tue, 15 Oct 2024 16:43:39 +0800
Subject: soc/mediatek/common: Config CAL_TOL_RATE and CAL_MAX_VAL in SoC
 folder

MT8196 has differenet configurations from other platforms. Make
CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse
common/pmif_clk.c

BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot

Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/mediatek/common/include/soc/pmif_sw.h | 6 ------
 src/soc/mediatek/common/pmif_clk.c            | 1 +
 2 files changed, 1 insertion(+), 6 deletions(-)

(limited to 'src/soc/mediatek/common')

diff --git a/src/soc/mediatek/common/include/soc/pmif_sw.h b/src/soc/mediatek/common/include/soc/pmif_sw.h
index ea26446298..c273c8e0fd 100644
--- a/src/soc/mediatek/common/include/soc/pmif_sw.h
+++ b/src/soc/mediatek/common/include/soc/pmif_sw.h
@@ -17,12 +17,6 @@ enum {
 	PMIF_WAIT_IDLE_US   = 1000,
 };
 
-/* calibation tolerance rate, unit: 0.1% */
-enum {
-	CAL_TOL_RATE = 40,
-	CAL_MAX_VAL = 0x7F,
-};
-
 u32 pmif_get_ulposc_freq_mhz(u32 cali_val);
 int pmif_clk_init(void);
 #endif /* __SOC_MEDIATEK_PMIF_SW_H__ */
diff --git a/src/soc/mediatek/common/pmif_clk.c b/src/soc/mediatek/common/pmif_clk.c
index cfd1dbce6b..f4e1d0eb7b 100644
--- a/src/soc/mediatek/common/pmif_clk.c
+++ b/src/soc/mediatek/common/pmif_clk.c
@@ -2,6 +2,7 @@
 
 #include <commonlib/helpers.h>
 #include <console/console.h>
+#include <soc/pmif.h>
 #include <soc/pmif_clk_common.h>
 #include <soc/pmif_sw.h>
 
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