From 62632ebf24cf50d77ab73e3458525561b77190da Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Tue, 27 Aug 2024 16:05:05 +0800 Subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115 Tested-by: build bot (Jenkins) Reviewed-by: Jianjun Wang Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/common/include/soc/pcie_common.h | 1 + src/soc/mediatek/common/pcie.c | 14 ++++++++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek/common') diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index 0f02ab7a90..c34bc4ee69 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -22,5 +22,6 @@ struct mtk_pcie_config { void mtk_pcie_domain_read_resources(struct device *dev); void mtk_pcie_domain_set_resources(struct device *dev); void mtk_pcie_domain_enable(struct device *dev); +void mtk_pcie_reset(uintptr_t base_reg, bool enable); #endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index 39714e161a..e796dc1ece 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -247,6 +247,16 @@ void mtk_pcie_domain_set_resources(struct device *dev) pci_domain_set_resources(dev); } +void mtk_pcie_reset(uintptr_t base_reg, bool enable) +{ + uint32_t flags = PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; + + if (enable) + setbits32p(base_reg + PCIE_RST_CTRL_REG, flags); + else + clrbits32p(base_reg + PCIE_RST_CTRL_REG, flags); +} + enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { if (!pci_root_bus()) @@ -291,7 +301,7 @@ void mtk_pcie_domain_enable(struct device *dev) printk(BIOS_WARNING, "%s: PCIe early init data not found, sleeping 100ms\n", __func__); - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(conf->base, true); } else { printk(BIOS_WARNING, "%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n", @@ -302,7 +312,7 @@ void mtk_pcie_domain_enable(struct device *dev) } /* De-assert reset signals */ - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); + mtk_pcie_reset(conf->base, false); if (!retry(100, (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & -- cgit v1.2.3