From 17180af69a95ad5823c501737d0ba2a0e849b4df Mon Sep 17 00:00:00 2001 From: Tristan Shieh Date: Mon, 2 Jul 2018 17:20:13 +0800 Subject: mediatek: Share PLL code among similar SOCs Refactor PLL code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c Signed-off-by: Tristan Shieh Reviewed-on: https://review.coreboot.org/27305 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/include/soc/pll_common.h | 73 ++++++++++++++++++++ src/soc/mediatek/common/pll.c | 88 ++++++++++++++++++++++++ 2 files changed, 161 insertions(+) create mode 100644 src/soc/mediatek/common/include/soc/pll_common.h create mode 100644 src/soc/mediatek/common/pll.c (limited to 'src/soc/mediatek/common') diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h new file mode 100644 index 0000000000..480371b67c --- /dev/null +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_PLL_COMMON_H +#define SOC_MEDIATEK_PLL_COMMON_H + +#include +#include + +/* These need to be macros for use in static initializers. */ +#define mtk_topckgen ((struct mtk_topckgen_regs *)CKSYS_BASE) +#define mtk_apmixed ((struct mtk_apmixed_regs *)APMIXED_BASE) + +#define PLL_PWR_ON (1 << 0) +#define PLL_EN (1 << 0) +#define PLL_ISO (1 << 1) +#define PLL_RSTB_SHIFT (24) +#define NO_RSTB_SHIFT (255) +#define PLL_PCW_CHG (1 << 31) +#define PLL_POSTDIV_MASK 0x7 + +struct mux { + void *reg; + void *upd_reg; + u8 mux_shift; + u8 mux_width; + u8 upd_shift; +}; + +struct pll { + void *reg; + void *pwr_reg; + void *div_reg; + void *pcw_reg; + const u32 *div_rate; + u8 rstb_shift; + u8 pcwbits; + u8 div_shift; + u8 pcw_shift; +}; + +#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \ + _pcw_reg, _pcw_shift, _div_rate) \ + [_id] = { \ + .reg = &mtk_apmixed->_reg, \ + .pwr_reg = &mtk_apmixed->_pwr_reg, \ + .rstb_shift = _rstb, \ + .pcwbits = _pcwbits, \ + .div_reg = &mtk_apmixed->_div_reg, \ + .div_shift = _div_shift, \ + .pcw_reg = &mtk_apmixed->_pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_rate = _div_rate, \ + } + +void pll_set_pcw_change(const struct pll *pll); +void mux_set_sel(const struct mux *mux, u32 sel); +int pll_set_rate(const struct pll *pll, u32 rate); +void mt_pll_init(void); + +#endif diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c new file mode 100644 index 0000000000..e087be38a2 --- /dev/null +++ b/src/soc/mediatek/common/pll.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) + +void mux_set_sel(const struct mux *mux, u32 sel) +{ + u32 mask = GENMASK(mux->mux_width - 1, 0); + u32 val = read32(mux->reg); + + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); + if (mux->upd_reg) + write32(mux->upd_reg, 1 << mux->upd_shift); +} + +static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv, + u32 freq) +{ + const u32 fin_hz = CLK26M_HZ; + const u32 *div_rate = pll->div_rate; + u32 val; + + assert(freq <= div_rate[0]); + assert(freq >= 1 * GHz / 16); + + for (val = 1; div_rate[val] != 0; val++) { + if (freq > div_rate[val]) + break; + } + val--; + *postdiv = val; + + /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */ + val += pll->pcwbits - PCW_INTEGER_BITS; + + *pcw = ((u64)freq << val) / fin_hz; +} + +static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv) +{ + u32 val; + + /* set postdiv */ + val = read32(pll->div_reg); + val &= ~(PLL_POSTDIV_MASK << pll->div_shift); + val |= postdiv << pll->div_shift; + + /* set postdiv and pcw at the same time if on the same register */ + if (pll->div_reg != pll->pcw_reg) { + write32(pll->div_reg, val); + val = read32(pll->pcw_reg); + } + + /* set pcw */ + val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); + val |= pcw << pll->pcw_shift; + write32(pll->pcw_reg, val); + + pll_set_pcw_change(pll); +} + +int pll_set_rate(const struct pll *pll, u32 rate) +{ + u32 pcw, postdiv; + + pll_calc_values(pll, &pcw, &postdiv, rate); + pll_set_rate_regs(pll, pcw, postdiv); + + return 0; +} -- cgit v1.2.3