From 00324b20e102f9f0f040077b584da12ba3fd699c Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Wed, 27 Jul 2022 16:12:12 +0800 Subject: soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay setting MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) --- src/soc/mediatek/common/spi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/mediatek/common') diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index f465027ab9..8bcc56e0cb 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -43,8 +43,9 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, SET32_BITFIELDS(&GET_SCK_REG(regs), SPI_CFG_SCK_LOW, sck_ticks - 1, SPI_CFG_SCK_HIGH, sck_ticks - 1); - SET32_BITFIELDS(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY, tick_dly, - SPI_CFG1_CS_IDLE, cs_ticks - 1); + SET32_BITFIELDS(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE, cs_ticks - 1); + + SET32_BITFIELDS(&GET_TICK_DLY_REG(regs), SPI_TICK_DLY, tick_dly); } static void spi_sw_reset(struct mtk_spi_regs *regs) -- cgit v1.2.3