From a4cad368a2996645d2ffc71425f49b246b0340ad Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Wed, 13 May 2020 10:01:14 +0800 Subject: soc/mediatek/mt8192: Add PLL and clock init support Add PLL and clock init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/common/pll.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'src/soc/mediatek/common/pll.c') diff --git a/src/soc/mediatek/common/pll.c b/src/soc/mediatek/common/pll.c index 35b03d845e..539d82cafe 100644 --- a/src/soc/mediatek/common/pll.c +++ b/src/soc/mediatek/common/pll.c @@ -12,9 +12,15 @@ void mux_set_sel(const struct mux *mux, u32 sel) u32 mask = GENMASK(mux->mux_width - 1, 0); u32 val = read32(mux->reg); - val &= ~(mask << mux->mux_shift); - val |= (sel & mask) << mux->mux_shift; - write32(mux->reg, val); + if (mux->set_reg && mux->clr_reg) { + write32(mux->clr_reg, mask << mux->mux_shift); + write32(mux->set_reg, sel << mux->mux_shift); + } else { + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); + } + if (mux->upd_reg) write32(mux->upd_reg, 1 << mux->upd_shift); } -- cgit v1.2.3